MT9079 Mitel Semiconductor, MT9079 Datasheet - Page 3

• Manufacturer Part Number: MT9079
• Description: CMOS ST-BUS FAMILY Advanced Controller for E1
• Manufacturer: Mitel Semiconductor

Pin Description
8-14 9-15 3-9
17-
DIP
15
16
20
1
2
3
4
5
6
7
-
-
Pin #
PLCC
19-
16
17
18
22
1
2
3
4
5
6
7
8
QFP
13-
39
40
41
42
43
44
10
11
12
16
1
2
AC3-AC
RESET RESET (Input): Low - maintains the device in a reset condition. High - normal
DLCLK Data Link Clock (Output): A 4 kHz clock signal used to clock out DL data (RxDL) on
CSTo0
ST/SC
D1-D7
Name
[ST S]
DSTo
RxDL
TxDL
AC4
[ST]
IRQ
SIO
V
NC
NC
D0
[P]
[S]
[P]
[P]
[P]
0
DD
operation. The MT9079 should be reset after power-up. The time constant for a
power-up reset circuit (see Figure 11) must be a minimum of five times the rise time of
the power supply. In normal operation, the RESET pin must be held low for a minimum
of 100 nsec. to reset the device.
Data ST-BUS (Output): A 2.048 Mbit/s serial output stream which contains the 30
PCM or data channels received from the PCM 30 line. See Figure 4b.
Receive Data Link (Output): A 4 kbit/s serial stream which is demultiplexed from a
selected national bit (non-frame alignment signal) of the PCM 30 receive signal.
Received DL data is clocked out on the rising edge of DLCLK, see Figure 20.
Transmit Data Link (Input): A 4 kbit/s serial stream which is multiplexed into a
selected national bit (non-frame alignment signal) of the PCM 30 transmit signal.
Transmit DL data is clocked in on the rising edge of internal clock IDCLK, see Figure
21.
its rising edge. It can also be used to clock DL data in and out of external serial
controllers (i.e., MT8952). See TxDL and RxDL pin descriptions.
No Connection.
Interrupt Request (Output): Low - interrupt request. High - no interrupt request.
IRQ is an open drain output that should be connected to V
An active CS signal is not required for this pin to function.
Data 0 (Three-state I/O): The least significant bit of the bidirectional data bus of the
parallel processor interface.
Serial Input/Output (Three state I/O): This pin function is used in serial controller
mode and can be configured as control data input/output for Intel operation (connect
to controller pin RxD). Input data is sampled LSB first on the rising edge of SCLK; data
is output LSB first on the falling edge of SCLK. It can also be configured as the control
data output for Motorola and National Microwire operation (data output MSB first on
the falling edge of SCLK). See CS pin description.
Control ST-BUS Zero (Output): A 2.048 Mbit/s serial status stream which provides
device status, performance monitoring, alarm status and phase status data.
Data 1 to Data 7 (Three-state I/O): These signals, combined with D0, form the
bidirectional data bus of the parallel processor interface (D7 is the most significant bit).
Positive Power Supply (Input): +5V
No Connection.
Address/Control 4 (Input): The most significant address and control input for the
non-multiplexed parallel processor interface.
ST-BUS/Serial Controller (Input): High - selects ST-BUS mode of operation.
Address/Control 3 to 0 (Inputs): Address and control inputs for the
non-multiplexed parallel processor interface. AC0 is the least significant input.
Low - selects serial controller mode of operation.
Description (see notes 1, 2 and 3)
10%.
DD
through a pull-up resistor.
MT9079
4-239