IDT72615L20J8 IDT, Integrated Device Technology Inc, IDT72615L20J8 Datasheet - Page 15

• Manufacturer Part Number: IDT72615L20J8
• Description: IC FIFO BY SYNC 512X18X2 68PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72615L20J8

• Function: Synchronous
• Memory Size: 18.4K (512 x 18 x 2)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72615L20J8

NOTES:
1. t
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes LOW.
NOTES:
1. t
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
(R/W
(R/W
(R/W
(R/W
the rising edge of CLK
and the rising edge of CLK
SKEW2
SKEW2
PAE
PAF
A
B
CLK
A
CLK
B
CLK
CLK
EN
EN
EN
EN
= 0)
= 1)
= 0)
= 1)
the minimum time between a rising CLK
is the minimum time between a rising CLK
AB
AB
B
A
A
A
A
B
B
A
t
t
CLKH
CLKH
B
is less than t
A
n words in FIFO
is less than t
t
SKEW2
t
t
CS
CS
t
t
Full - (m+1) words in FIFO
CLKL
CLKL
SKEW
WRITE
(1)
WRITE
SKEW2
, then PAE
A
Figure 12. A → → → → → B Programmable Almost-Empty Flag Timing
, then PAF
Figure 13. A → → → → → B Programmable Almost-Full Flag Timing
edge and a rising CLK
B
t
t
CH
CH
edge and a rising CLK
AB
may not go HIGH until the next CLKB rising edge.
t
PAE
AB
may not go HIGH until the next CLK
(2)
B
edge for PAE
A
t
PAF
edge for PAF
15
AB
AB
to change during that clock cycle. If the time between the rising edge of CLK
to change during that clock cycle. If the time between the rising edge of CLK
n+1 words in FIFO
t
CS
A
Full - m words in FIFO
rising edge.
READ
t
CS
t
CH
READ
INDUSTRIAL TEMPERATURE RANGE
t
CH
(2)
t
PAF
t
PAE
2704 drw 15
2704 drw 16
A
and
B