IDT72V3612L12PFG IDT, Integrated Device Technology Inc, IDT72V3612L12PFG Datasheet - Page 11

• Manufacturer Part Number: IDT72V3612L12PFG
• Description: IC FIFO 64X36X2 12NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3612L12PFG

• Function: Asynchronous
• Memory Size: 4.6K (64 x 36 x2)
• Data Rate: 83MHz
• Access Time: 12ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 72V3612L12PFG

and read operations and are not related to high-impedance control of the data
outputs. If a port enable is LOW during a clock cycle, the port chip select and
write/read select may change states during the setup and hold time window of
the cycle.
SYNCHRONIZED FIFO FLAGS
This is done to improve flag reliability by reducing the probability of
metastable events on the output when CLKA and CLKB operate asynchro-
nously to one another. EFA, AEA, FFA, and AFA are synchronized by
CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and
5 show the relationship of each port flag to FIFO1 and FIFO2.
EMPTY FLAGS (EFA, EFB)
data from its array. When the Empty Flag is HIGH, new data can be read
to the FIFO output register. When the Empty Flag is LOW, the FIFO is empty
and attempted FIFO reads are ignored.
clocked to the output register. The state machine that controls an Empty
Flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO memory status is empty, empty+1, or empty+2. A word
written to a FIFO can be read to the FIFO output register in a minimum of
three cycles of the Empty Flag synchronizing clock. Therefore, an Empty
Flag is LOW if a word in memory is the next data to be sent to the FIFO output
register and two cycles of the port clock that reads data from the FIFO have
not elapsed since the time the word was written. The Empty Flag of the FIFO
is set HIGH by the second LOW-to-HIGH transition of the synchronizing
clock, and the new data word can be read to the FIFO output register in the
following cycle.
the first synchronization cycle of a write if the clock transition occurs at time
t
be the first synchronization cycle (see Figure 7 and Figure 8).
FULL FLAG (FFA, FFB)
to its array. When the Full Flag is HIGH, a memory location is free in the
FIFO to receive new data. No memory locations are free when the Full Flag
is LOW and attempted writes to the FIFO are ignored.
state machine that controls a Full Flag monitors a write-pointer and read pointer
comparator that indicates when the FIFO memory status is full, full-1, or full-2.
TABLE 4 – FIFO1 FLAG OPERATION
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag offset register.
SKEW1
IDT72V3612 3.3V, CMOS SyncBiFIFO
64 x 36 x 2
Each FIFO is synchronized to its port clock through two flip-flop stages.
The Empty Flag of a FIFO is synchronized to the port clock that reads
The read pointer of a FIFO is incremented each time a new word is
A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins
The Full Flag of a FIFO is synchronized to the port clock that writes data
Each time a word is written to a FIFO, the write pointer is incremented. The
Number of Words
(X+1) to [64-(X+1)]
in the FIFO1
or greater after the write. Otherwise, the subsequent clock cycle can
(64-X) to 63
1 to X
64
0
(1)
EFB
Synchronized
H
H
H
H
L
to CLKB
AEB
TM
H
H
H
L
L
Synchronized
AFA
H
H
H
L
L
to CLKA
FFA
H
H
H
H
L
11
From the time a word is read from a FIFO, the previous memory location is ready
to be written in a minimum of three cycles of the Full Flag synchronizing clock.
Therefore, a Full Flag is LOW if less than two cycles of the Full Flag synchronizing
clock have elapsed since the next memory write location has been read. The
second LOW-to-HIGH transition on the Full Flag synchronization clock after the
read sets the Full Flag HIGH and the data can be written in the following clock
cycle.
first synchronization cycle of a read if the clock transition occurs at time
t
be the first synchronization cycle (see Figure 9 and Figure 10).
ALMOST EMPTY FLAGS (AEA, AEB)
reads data from its array. The state machine that controls an Almost-Empty
flag monitors a write-pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-empty state is defined by the value of the Almost-Full and Almost-
Empty Offset register (X). This register is loaded with one of four preset
values during a device reset (see Reset section). An Almost-Empty flag is
LOW when the FIFO contains X or less words in memory and is HIGH when
the FIFO contains (X+1) or more words.
ing clocks are required after a FIFO write for the Almost-Empty flag to reflect
the new level of fill. Therefore, the Almost-Empty flag of a FIFO containing
(X+1) or more words remains LOW if two cycles of the synchronizing clock
have not elapsed since the write that filled the memory to the (X+1) level.
An Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition
of the synchronizing clock after the FIFO write that fills memory to the (X+1)
level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing
clock begins the first synchronization cycle if it occurs at time t
greater after the write that fills the FIFO to (X+1) words. Otherwise, the
subsequent synchronizing clock cycle can be the first synchronization cycle
(see Figure 11 and 12).
ALMOST FULL FLAGS (AFA, AFB)
writes data to its array. The state machine that controls an Almost-Full flag
monitors a write-pointer and read-pointer comparator that indicates when the
FIFO memory status is almost-full, almost-full-1, or almost-full-2. The almost-full
state is defined by the value of the Almost-Full and Almost-Empty Offset register
(X). This register is loaded with one of four preset values during a device reset
(see Reset section). An Almost-Full flag is LOW when the FIFO contains (64-
TABLE 5 – FIFO2 FLAG OPERATION
SKEW1
A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the
The Almost-Empty flag of a FIFO is synchronized to the port clock that
Number of Words
(X+1) to [64-(X+1)]
Two LOW-to-HIGH transitions of the Almost-Empty flag synchroniz-
The Almost-Full flag of a FIFO is synchronized to the port clock that
in the FIFO2
or greater after the read. Otherwise, the subsequent clock cycle can
(64-X) to 63
1 to X
64
0
(1)
COMMERCIAL TEMPERATURE RANGE
EFA
Synchronized
H
H
H
H
L
to CLKB
AEA
H
H
H
L
L
FEBRUARY 12, 2009
Synchronized
AFB
H
H
H
L
L
to CLKA
SKEW2
FFB
H
H
H
H
L
or