IDT723614L15PF IDT, Integrated Device Technology Inc, IDT723614L15PF Datasheet

IDT723614L15PF

Manufacturer Part Number

IDT723614L15PF

Description

IC FIFO CLOCKED 64X36X2 120QFP

Manufacturer

IDT, Integrated Device Technology Inc

Series

7200r

Datasheet

1.IDT723614L20PF8.pdf (32 pages)

Specifications of IDT723614L15PF

Function

Synchronous

Memory Size

4.6K (64 x 36 x2)

Data Rate

67MHz

Access Time

15ns

Voltage - Supply

4.5 V ~ 5.5 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

120-TQFP, 120-VQFP

Configuration

Dual

Density

4.5Kb

Access Time (max)

10ns

Word Size

36b

Organization

64x36x2

Sync/async

Synchronous

Expandable

Bus Direction

Bi-Directional

Package Type

TQFP

Clock Freq (max)

66.7MHz

Operating Supply Voltage (typ)

Operating Supply Voltage (min)

4.5V

Operating Supply Voltage (max)

5.5V

Supply Current

1mA

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

120

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

723614L15PF

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

IDT723614L15PF

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

IDT723614L15PF8

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Current page: 1 of 32
Download datasheet (309Kb)

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FEATURES:

• • • • •

FUNCTIONAL BLOCK DIAGRAM

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBIFIFO is a trademark of Integrated Device Technology, Inc.

Free-running CLKA and CLKB can be asynchronous or

coincident (simultaneous reading and writing of data on a

single clock edge is permitted)

Two independent clocked FIFOs (64 x 36 storage capacity each)

buffering data in opposite directions

Mailbox bypass Register for each FIFO

Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),

and 9 bits (byte)

Selection of Big- or Little-Endian format for word and byte bus

sizes

Three modes of byte-order swapping on port B

EVEN

PEFA

MBF2

ODD/

- A

PGA

AFA

FFA

FS0

FS1

AEA

RST

EFA

Control

Device

CLKA

W/RA

MBA

CSA

ENA

CMOS SyncBiFIFO

BUS-MATCHING AND BYTE SWAPPING

64 x 36 x 2

Control

Port-A

Logic

FIFO1

FIFO2

Gen/Check

Parity

64 x 36

ARRAY

Pointer

RAM

Write

Status Flag

Programmable Flag

Mail 1

Logic

• • • • •

Offset Register

Pointer

Read

64 x 36

Programmable Almost-Full and Almost-Empty flags

Microprocessor interface control logic

EFA, FFA, AEA, and AFA flags synchronized by CLKA

EFB, FFB, AEB, and AFB flags synchronized by CLKB

Passive parity checking on each port

Parity generation can be selected for each port

Supports clock frequencies up to 67 MHz

Fast access times of 10 ns

Available in 132-pin plastic quad flat package (PQF) or space-

saving 120-pin thin quad flat package (TQFP)

Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available

Green parts available, see ordering information

ARRAY

Pointer

RAM

Read

Status Flag

Logic

Mail 2

WITH

Pointer

Gen/Check

Write

Parity

Control

Port-B

Logic

CLKB

CSB

W/RB

ENB

SIZ0

SIZ1

SW0

SW1

JANUARY 2009

MBF1

PGB

PEFB

EFB

AEB

FFB

AFB

3146 drw01

IDT723614

-B

DSC-3146/3

Related parts for IDT723614L15PF

IDT723614L15PF Summary of contents

Page 1

FEATURES: • • • • • Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • • • • • Two independent clocked FIFOs ( ...

Page 2

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING DESCRIPTION: The IDT723614 is a monolithic, high-speed, low-power CMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 67MHz and has read ...

Page 3

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING This device is a clocked FIFO, which means each port employs a synchro- nous interface. All data transfers through a port are gated ...

Page 4

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING PIN DESCRIPTION Symbol Name A0-A35 Port A Data AEA Port A Almost-Empty Flag AEB Port B Almost-Empty Flag AFA Port A Almost-Full Flag ...

Page 5

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING PIN DESCRIPTION (CONTINUED) Symbol Name ODD/ Odd/Even Parity EVEN Select PEFA Port A Parity Error Flag (Port A) PEFB Port B Parity Error ...

Page 6

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED) Symbol V Supply Voltage Range CC V (2) Input Voltage Range I ...

Page 7

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING 400 350 f data = 1 25° 300 L 250 200 150 100 ...

Page 8

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Commercial 5.0V ±10 0°C to +70°C; ...

Page 9

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C (Commercial 5.0V ±10 0°C to +70°C; ...

Page 10

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING SIGNAL DESCRIPTIONS RESET The IDT723614 is reset by taking the Reset (RST) input LOW for at least four port A clock (CLKA) and ...

Page 11

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING greater after the write that fills the FIFO to (X+1) long words. SKEW2 Otherwise, the subsequent synchronizing clock cycle can be ...

Page 12

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING rising CLKB edge when a port B read is selected by CSB, W/RB, and ENB with both SIZ1 and SIZ0 HIGH. ...

Page 13

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING BYTE ORDER ON PORT A: BE SIZ1 SIZ0 SIZ1 SIZ0 SIZ1 SIZ0 ...

Page 14

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING PARITY CHECKING The port A inputs (A0-A35) and port B inputs (B0-B35) each have four parity trees to check the parity of incoming ...

Page 15

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING SW1 SW0 SW1 SW0 L H SW1 SW0 H L SW1 SW0 H H A35⎯A27 A26⎯A18 ...

Page 16

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLKA CLKB t RSTS RST FS1,FS0 FFA EFA FFB EFB t RSF MBF1, MBF2 AEA AFA AEB AFB Figure 5. Device Reset Loading ...

Page 17

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLK t t CLKH CLKL CLKA FFA HIGH t ENS CSA t ENS W/RA t ENS MBA t ENS ENA t DS ...

Page 18

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLKB FFB HIGH CSB W/RB ENB SW1, SW0 t SZS t SZH SZS SZH SIZ1, SIZ0 (0, 1) Little- B0-B17 ...

Page 19

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLKB FFB HIGH t ENS CSB t ENS W/RB t ENH ENB t SWS SW1, SW0 SZS SZS SZH BE ...

Page 20

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLKB EFB HIGH CSB W/RB ENB SW1, SW0 t SZH t SZS SZH SZS SIZ1, (0,0) NOT (1,1) SIZ0 PGB, ...

Page 21

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLKB EFB HIGH CSB W/RB ENB SW1, SW0 t t SZH SZS BE t SZH t SZS SIZ1, (0,1) NOT (1,1) SIZ0 PGB, ...

Page 22

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLKB EFB HIGH CSB W/RB t ENS ENB t SWS SW1, SW0 t t SZS SZH SZS SZH SIZ1, (1,0) ...

Page 23

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLK t t CLKH CLKL CLKA EFA HIGH CSA W/RA MBA ENA t MDV A35 PGA, ODD/ EVEN ...

Page 24

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLKB CSB LOW W/RB HIGH t ENS SIZ1, SIZ0 t ENS ENB FFB HIGH B35 SKEW1 (1) t ...

Page 25

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLK t t CLKH CLKL CLKB CSB LOW LOW W/RB SIZ1, LOW SIZ0 t ENS ENB EFB HIGH B0 - B35 Previous ...

Page 26

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLK t t CLKL CLKH CLKA CSA LOW LOW W/RA LOW MBA t ENS ENA EFA HIGH A0 - A35 Previous Word ...

Page 27

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLKB t ENS ENB CLKA AEA ENA NOTES: is the minimum time between a rising CLKB edge and a rising CLKA edge for ...

Page 28

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLKA t ENS CSA W/RA MBA ENA A0 - A35 CLKB MBF1 CSB W/RB SIZ1, SIZ0 ENB B35 FIFO1 ...

Page 29

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING CLKB CSB W/RB SIZ1, SIZ0 ENB B0 - B35 CLKA MBF2 CSA W/RA MBA ENA A35 FIFO2 Output Register ...

Page 30

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING ODD/ EVEN W/RB SIZ1, SIZ0 PGB t POPE PEFB Valid Figure 25. ODD/ EVEN ODD/ EVEN CSA LOW W/RA MBA PGA t EN ...

Page 31

IDT723614 CMOS SYNCBIFIFO™ ™ ™ ™ ™ WITH BUS-MATCHING AND BYTE SWAPPING From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable ...

Page 32

ORDERING INFORMATION X XX XXXXXX Device Type Power Speed NOTES: 1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts are available. For ...

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