IDT723612L15PQF IDT, Integrated Device Technology Inc, IDT723612L15PQF Datasheet
IDT723612L15PQF
Specifications of IDT723612L15PQF
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IDT723612L15PQF Summary of contents
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FEATURES • • • • • Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • • • • • Two independent clocked FIFOs ( ...
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IDT723612 TM CMOS SYNCBiFIFO Almost-Empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a ...
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IDT723612 CMOS SYNCBiFIFO PIN CONFIGURATIONS (CONTINUED GND ...
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IDT723612 TM CMOS SYNCBiFIFO PIN DESCRIPTION Symbol Name I/O A0-A35 Port-A Data AEA Almost-Empty Flag (Port A) AEB Port-B Almost-Empty Flag (Port B) AFA Port-A Almost-Full Flag (Port A) AFB Port-B Almost-Empty Flag (Port B) ...
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IDT723612 CMOS SYNCBiFIFO PIN DESCRIPTION (CONTINUED) Symbol Name ODD/ Odd/Even Parity EVEN Select PEFA Port-A Parity Error Flag (Port A) PEFB Port-B Parity Error Flag (Port B) PGA Port-A Parity PGB Port-B Parity RST ...
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IDT723612 TM CMOS SYNCBiFIFO ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I V (2) Output Voltage Range O I Input ...
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IDT723612 CMOS SYNCBiFIFO 400 350 f data 300 250 200 150 100 Figure 1. Typical Characteristics: Supply Current vs Clock Frequency CALCULATING POWER DISSIPATION The I ...
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IDT723612 TM CMOS SYNCBiFIFO ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Commercial 5.0V ±10 0°C to +70°C; Industrial Symbol Parameter f Clock ...
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IDT723612 CMOS SYNCBiFIFO SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE 30PF (Commercial 5.0V ±10 0°C to +70°C; Industrial Symbol t ...
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IDT723612 TM CMOS SYNCBiFIFO SIGNAL DESCRIPTIONS RESET The IDT723612 is reset by taking the Reset (RST) input LOW for at least four port-A clock (CLKA) and four port-B Clock (CLKB) LOW-to-HIGH transitions. The Reset input ...
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IDT723612 CMOS SYNCBiFIFO The setup and hold time constraints to the port clocks for the port Chip Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write and read operations and ...
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IDT723612 TM CMOS SYNCBiFIFO SRAM status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined by the value of the Almost-Full and Almost-Empty Offset register (X). This register is loaded with one of four ...
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IDT723612 CMOS SYNCBiFIFO CLKA CLKB t RSTS RST FS1,FS0 FFA EFA FFB EFB AEA AFA t RSF MBF1, MBF2 AEB AFB Figure 2. Device Reset Loading the X Register with the Value of Eight ...
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IDT723612 TM CMOS SYNCBiFIFO CLK t t CLKL CLKH CLKA FFA HIGH t ENS1 CSA t ENS1 W/RA t ENS3 MBA t ENS2 ENA A35 ODD/ EVEN PEFA NOTE: 1. ...
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IDT723612 CMOS SYNCBiFIFO CLK t t CLKH CLKL CLKB EFB HIGH CSB W/RB MBB ENB t MDV B35 PGB, ODD/ EVEN NOTE: 1. Read from FIFO1. t CLK t ...
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IDT723612 TM CMOS SYNCBiFIFO CLKA CSA LOW WRA HIGH t t ENS3 MBA t t ENS2 ENA FFA HIGH A35 W1 t SKEW1 CLKB EFB FIFO1 Empty CSB LOW ...
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IDT723612 CMOS SYNCBiFIFO CLKB CSB LOW W/RB HIGH t t ENS3 MBB t t ENS2 ENB FFB HIGH B35 W1 t SKEW1 CLKA EFA FIFO2 Empty CSA LOW ...
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IDT723612 TM CMOS SYNCBiFIFO CLK t t CLKH CLKL CLKB CSB LOW LOW W/RB MBB LOW t ENS2 ENB EFB HIGH B0 - B35 Previous Word in FIFO1 Output Register CLKA FFA CSA LOW ...
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IDT723612 CMOS SYNCBiFIFO CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA MBA LOW t ENS2 ENA EFA HIGH A0 - A35 Previous Word in FIFO2 Output Register CLKB FFB CSB LOW ...
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IDT723612 TM CMOS SYNCBiFIFO CLKB t ENS2 ENB CLKA AEA ENA NOTES: is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA ...
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IDT723612 CMOS SYNCBiFIFO CLKA t ENS1 CSA t ENS1 W/RA t ENS1 MBA t ENS1 ENA A0 - A35 CLKB MBF1 CSB W/RB MBB ENB B35 FIFO1 Output Register NOTE: ...
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IDT723612 TM CMOS SYNCBiFIFO NOTE: 1. Port-A parity generation off (PGA = LOW). ODD/ EVEN W/RA MBA PGA t POPE PEFA Valid NOTE: 1. ENA is HIGH, and CSA is LOW. W1 (Remains valid in ...
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IDT723612 CMOS SYNCBiFIFO ODD/ EVEN W/RB MBB PGB t PEFB Valid NOTE: 1. ENB is HIGH, and CSB is LOW. Figure 18. ODD/ EVEN ODD/ EVEN CSA LOW W/RA MBA PGA t EN A8, ...
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IDT723612 TM CMOS SYNCBiFIFO PARAMETER MEASUREMENT INFORMATION From Output Under Test 1.5 V Timing Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 ...
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ORDERING INFORMATION XXXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts are available. For ...