IDT72V3614L15PF IDT, Integrated Device Technology Inc, IDT72V3614L15PF Datasheet

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IDT72V3614L15PF

Manufacturer Part Number
IDT72V3614L15PF
Description
IC FIFO 64X36X2 15NS 120QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V3614L15PF

Function
Asynchronous, Synchronous
Memory Size
4.6K (64 x 36 x2)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
120-TQFP, 120-VQFP
Configuration
Dual
Density
4.5Kb
Access Time (max)
10ns
Word Size
36b
Organization
64x36x2
Sync/async
Synchronous
Expandable
No
Bus Direction
Bi-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
500mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
120
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V3614L15PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V3614L15PF
Manufacturer:
IDT
Quantity:
5
Part Number:
IDT72V3614L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V3614L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
FEATURES:
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
FUNCTIONAL BLOCK DIAGRAM
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
Two independent clocked FIFOs (64 x 36 storage capacity each)
buffering data in opposite directions
Supports clock frequencies up to 83 MHz
Fast access times of 8 ns
Free-running CLKA and CLKB can be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single
clock edge is permitted)
Mailbox bypass Register for each FIFO
Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)
Selection of Big- or Little-Endian format for word and byte bus
sizes
A
0
EVEN
PEFA
MBF2
ODD/
- A
PGA
AFA
FS0
RST
FFA
FS1
AEA
EFA
35
Control
Device
CLKA
W/RA
MBA
CSA
ENA
36
Control
Port-A
Logic
3.3 VOLT CMOS SyncBiFIFO
BUS-MATCHING AND BYTE SWAPPING
64 x 36 x 2
FIFO1
FIFO2
Gen/Check
Parity
64 x 36
ARRAY
RAM
Pointer
Write
Status Flag
Register
Programmable Flag
Mail 1
Logic
Offset Register
1 1
Pointer
Read
64 x 36
ARRAY
Pointer
RAM
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
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Read
Status Flag
Three modes of byte-order swapping on port B
Programmable Almost-Full and Almost-Empty flags
Microprocessor interface control logic
EFA , FFA , AEA , and AFA flags synchronized by CLKA
EFB , FFB , AEB , and AFB flags synchronized by CLKB
Passive parity checking on each port
Parity generation can be selected for each port
Available in 132-pin plastic quad flat package (PQF), or space
saving 120-pin thin quad flat package (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723614
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
Register
Logic
Mail 2
Pointer
Gen/Check
Write
Parity
4663 drw 01
TM
WITH
Control
Port-B
Logic
36
36
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
FEBRUARY 2009
MBF1
PGB
PEFB
EFB
AEB
FFB
AFB
B
IDT72V3614
0
-B
35
DSC-4663/3

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IDT72V3614L15PF Summary of contents

Page 1

FEATURES: • • • • • Two independent clocked FIFOs ( storage capacity each) buffering data in opposite directions • • • • • Supports clock frequencies MHz • • • • • Fast access ...

Page 2

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING DESCRIPTION: The IDT72V3614 is a pin and functionally compatible version of the IDT723614, designed to run off a 3.3V supply for exceptionally low power consumption. This ...

Page 3

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING DESCRIPTION (CONTINUED): This device is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the ...

Page 4

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING PIN DESCRIPTION Symbol Name I/O A0-A35 Port A Data I/O 36-bit bidirectional data port for side A. AEA Port A Almost- O Programmable Almost-Empty flag synchronized ...

Page 5

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING PIN DESCRIPTION (Continued) Symbol Name I/O MBF2 MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to ...

Page 6

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC V (2) Input Voltage Range I (2) V Output ...

Page 7

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on ...

Page 8

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Commercial: Vcc=3.3V ± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; T Symbol Parameter ...

Page 9

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C Commercial: Vcc=3.3V ± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; T Symbol Parameter ...

Page 10

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING SIGNAL DESCRIPTIONS RESET The IDT72V3614 is reset by taking the Reset (RST) input LOW for at least four port A clock (CLKA) and four port B ...

Page 11

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING TABLE 1 – FLAG PROGRAMMING ALMOST-FULL AND RST FS1 FS0 ALMOST-EMPTY FLAG OFFSET REGISTER (X) ↑ ↑ ↑ ↑ L ...

Page 12

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING cycle if it occurs at time t or greater after the write that fills the FIFO to (X+1) SKEW2 long words. Otherwise, the subsequent synchronizing clock ...

Page 13

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING The order of the bytes are rearranged within the long word, but the bit order within the bytes remains constant. Byte arrangement is chosen by the ...

Page 14

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING BYTE ORDER ON PORT A: BYTE ORDER ON PORT B: BE SIZ1 SIZ0 SIZ1 SIZ0 SIZ1 SIZ0 H ...

Page 15

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING B35⎯B27 BE SIZ1 SIZ0 B35⎯B27 B35⎯B27 B35⎯B27 CLKB SIZ0 SIZ1 BE (1) Either a HIGH or LOW can be applied to a "don't ...

Page 16

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING SW1 SW0 SW1 SW0 L H SW1 SW0 H L SW1 SW0 H H WITH A35⎯A27 A26⎯A18 B35⎯B27 ...

Page 17

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLKA CLKB t RSTS RST FS1,FS0 FFA EFA FFB EFB t RSF MBF1, MBF2 AEA AFA AEB AFB Figure 5. Device Reset and Loading the X ...

Page 18

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLK t t CLKH CLKL CLKA FFA HIGH t ENS CSA t ENS W/RA t ENS MBA t ENS ENA A35 ...

Page 19

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLKB FFB HIGH CSB W/RB ENB SW1, SW0 t SZS t SZH SZS SZH SIZ1, SIZ0 (0, 1) Little- B0-B17 Endian Big- B18-B35 ...

Page 20

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLKB FFB HIGH t ENS CSB t ENS W/RB t ENS ENB t SWS SW1, SW0 SZS SZS SZH ...

Page 21

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLKB EFB HIGH CSB W/RB ENB SW1, SW0 t t SZH SZS BE t SZH t SZS SIZ1, (0,0) NOT (1,1) SIZ0 PGB, ODD/ EVEN B0-B35 ...

Page 22

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLKB EFB HIGH CSB W/RB ENB SW1, SW0 t t SZH SZS BE t SZH t SZS SIZ1, (0,1) SIZ0 PGB, ODD/ EVEN Little- B0-B17 (2) ...

Page 23

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLKB EFB HIGH CSB W/RB ENB t SW1, SW0 t t SZS SZH SZS SZH SIZ1, (1,0) SIZ0 Not (1,1) t PGS PGB, ...

Page 24

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLK t CLKH t CLKL CLKA EFA HIGH CSA W/RA MBA ENA t MDV A35 PGA, ODD/ EVEN NOTE: 1. Read ...

Page 25

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLKB CSB LOW WRB HIGH t t ENS ENH SIZ1, SIZ0 t t ENS ENH ENB FFB HIGH B35 ...

Page 26

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLK t t CLKH CLKL CLKB LOW CSB W/RB LOW SIZ1, LOW SIZ0 t ENS ENB EFB HIGH B0 - B35 Previous Word in FIFO1 ...

Page 27

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS ENA EFA HIGH Previous Word in FIFO2 Output Register A0 - ...

Page 28

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLKB t t ENS ENH ENB t SKEW2 CLKA AEA X Long Words in FIFO2 ENA NOTES: is the minimum time between a rising CLKB edge ...

Page 29

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLKA t ENS CSA W/RA MBA ENA A0 - A35 CLKB MBF1 CSB W/RB SIZ1, SIZ0 ENB t EN FIFO1 Output Register B0 - B35 NOTE: ...

Page 30

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING CLKB CSB W/RB SIZ1, SIZ0 ENB B0 - B35 CLKA MBF2 CSA W/RA MBA ENA t EN FIFO2 Output Register A0 - A35 NOTE: 1. Port-A ...

Page 31

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING ODD/ EVEN W/RB SIZ1, SIZ0 PGB t POPE PEFB Valid Figure 25. ODD/ EVEN ODD/ EVEN CSA LOW W/RA MBA PGA t EN A8, A17, A26, ...

Page 32

TM IDT72V3614 3.3V, CMOS SyncBiFIFO BUS-MATCHING AND BYTE SWAPPING PARAMETER MEASUREMENT INFORMATION From Output Under Test Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES ...

Page 33

ORDERING INFORMATION X XX XXXXXX Device Type Power Speed NOTES: 1. Industrial temperature range is available by special order. 2. Green parts are available. For specific speeds and packages contact your sales office. DATASHEET DOCUMENT HISTORY 07/10/2000 pg. 1. 05/27/2003 ...

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