IDT72V3611L15PF IDT, Integrated Device Technology Inc, IDT72V3611L15PF Datasheet

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IDT72V3611L15PF

Manufacturer Part Number
IDT72V3611L15PF
Description
IC FIFO SYNC 64X36 15NS 120-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V3611L15PF

Function
Synchronous
Memory Size
2.3K (64 x 36)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V3611L15PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V3611L15PF
Manufacturer:
IDT
Quantity:
6
Part Number:
IDT72V3611L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V3611L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
FEATURES:
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FUNCTIONAL BLOCK DIAGRAM
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
coincident (permits simultaneous reading and writing of
CLKB
64 x 36 storage capacity
Supports clock frequencies up to 67MHz
Fast access times of 10ns
Free-running CLKA and CLKB may be asynchronous or
data on a single clock edge)
Synchronous data buffering from Port A to Port B
Mailbox bypass register in each direction
Programmable Almost-Full (AF) and Almost-Empty (AE) flags
Microprocessor Interface Control Logic
Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
Empty Flag (EF) and Almost-Empty (AE) flags synchronized by
Passive parity checking on each Port
Parity Generation can be selected for each Port
A
0
ODD/
EVEN
PEFA
MBF2
PGA
- A
RST
FS
FS
AF
FF
35
0
1
Reset
CLKA
W/RA
Logic
MBA
CSA
ENA
36
Control
Port-A
Logic
FIFO
3.3 VOLT CMOS SyncFIFO
64 x 36
Gen/Check
Parity
Pointer
Write
Programmable
Status Flag
Flag Offset
Register
Registers
64 x 36
ARRAY
Mail 1
Logic
RAM
JUNE 7 , 2005
Pointer
Read
Register
Mail 2
1
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DESCRIPTION:
IDT723611, designed to run off a 3.3V supply for exceptionally low power
consumption. This device is a monolithic, high-speed, low-power, CMOS
Synchronous (clocked) FIFO memory which supports clock frequencies up to
67MHz and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO
buffers data from Port A to Port B. The FIFO operates in IDT Standard mode
and has flags to indicate empty and full conditions, and two programmable flags,
Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected number
Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving
120-pin Thin Quad Flatpack (PF)
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Pin and functionally compatible version of the 5V operating
IDT723611
Green parts available, see ordering information
The IDT72V3611 is a pin and functionally compatible version of the
Gen/Check
Parity
TM
Control
Port-B
Logic
FEBRUARY 2009
IDT72V3611
36
4657 drw01
MBF1
PGB
B
EF
CLKB
CSB
W/RB
ENB
MBB
PEFB
AE
0
- B
DSC-4657/3
35

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IDT72V3611L15PF Summary of contents

Page 1

FEATURES: • • • • • storage capacity • • • • • Supports clock frequencies up to 67MHz • • • • • Fast access times of 10ns • • • • • Free-running CLKA and ...

Page 2

IDT72V3611 3.3V, CMOS SyncFIFO DESCRIPTION (CONTINUED) of words is stored in memory. Communication between each port can take place through two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has ...

Page 3

IDT72V3611 3.3V, CMOS SyncFIFO PIN CONFIGURATION (CONTINUED) GND GND ...

Page 4

IDT72V3611 3.3V, CMOS SyncFIFO PIN DESCRIPTION Symbol Name A0-A35 Port-A Data AE Almost-Empty Flag AF Almost-Full Flag B0-B35 Port-B Data. CLKA Port-A Clock CLKB Port-B Clock CSA Port-A Chip Select CSB Port-B Chip Select EF Empty ...

Page 5

IDT72V3611 3.3V, CMOS SyncFIFO PIN DESCRIPTION (CONTINUED) Symbol Name PEFB Port-B Parity Error Flag (Port B) PGA Port-A Parity Generation PGB Port-B Parity Generation RST Reset W/RA Port-A Write/Read Select W/RB Port-B Write/Read Select I/O When ...

Page 6

IDT72V3611 3.3V, CMOS SyncFIFO ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC V (2) Input Voltage Range I (2) V Output Voltage Range O I Input Clamp ...

Page 7

IDT72V3611 3.3V, CMOS SyncFIFO DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I data for the graph was taken while simultaneously reading and writing the FIFO on the IDT72V3611 with CLKA and CLKB operating at frequency ...

Page 8

IDT72V3611 3.3V, CMOS SyncFIFO TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURES Symbol Parameter f Clock Frequency, CLKA or CLKB S t Clock Cycle Time, CLKA or CLKB CLK t Pulse Duration, ...

Page 9

IDT72V3611 3.3V, CMOS SyncFIFO SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C Symbol Parameter f Clock Frequency, CLKA or CLKB S t Access Time, CLKB↑ to B0-B35 A Propagation Delay Time, ...

Page 10

IDT72V3611 3.3V, CMOS SyncFIFO SIGNAL DESCRIPTION RESET ( RST ) The IDT72V3611 is reset by taking the Reset (RST) input LOW for at least four port-A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH transitions. ...

Page 11

IDT72V3611 3.3V, CMOS SyncFIFO SYNCHRONIZED FIFO FLAGS Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve the flags’ reliability by reducing the probability of metastable events on ...

Page 12

IDT72V3611 3.3V, CMOS SyncFIFO present on the port-A data (A0-A35) outputs when they are active. The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port-B read is selected by ...

Page 13

IDT72V3611 3.3V, CMOS SyncFIFO CLKA CLKB t RSTS RST FS1,FS0 RSF MBF1, MBF2 Figure 2. Device Reset and Loading the X Register with the Value of Eight t CLK t t ...

Page 14

IDT72V3611 3.3V, CMOS SyncFIFO CLK t t CLKH CLKL CLKB EF HIGH CSB W/RB t ENS2 MBB ENB t MDV B35 PGB, ODD/ EVEN CLKA CSA LOW WRA HIGH t ENS3 ...

Page 15

IDT72V3611 3.3V, CMOS SyncFIFO CLK t t CLKH CLKL CLKB LOW CSB LOW W/RB LOW MBB t ENS2 ENB EFB HIGH B0 -B35 Previous Word in FIFO Output Register CLKA FF CSA LOW WRA HIGH ...

Page 16

IDT72V3611 3.3V, CMOS SyncFIFO CLKA t t ENS2 ENH2 ENA t PAF AF [64-(X+1)] Words in FIFO CLKB ENB NOTES: is the minimum time between a rising CLKA edge and a rising CLKB edge for AF ...

Page 17

IDT72V3611 3.3V, CMOS SyncFIFO CLKB t ENS1 CSB t ENS1 W/RB t ENS1 MBB t ENS1 ENB B0 - B35 CLKA MBF2 CSA W/RA MBA ENA A35 NOTE: 1. Port-A parity generation ...

Page 18

IDT72V3611 3.3V, CMOS SyncFIFO ODD/ EVEN CSA LOW W/RA MBA PGA t EN A8, A17, A26, A35 NOTE: 1. ENA = H. Figure 13. Parity Generation Timing when reading from the Mail2 Register ODD/ EVEN CSB ...

Page 19

IDT72V3611 3.3V, CMOS SyncFIFO PARAMETER MEASUREMENT INFORMATION From Output Under Test Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 PZL ...

Page 20

ORDERING INFORMATION XXXXXX X XX Device Type Power Speed Package NOTES: 1. Industrial temperature range is available by special order. 2. Green parts are available. For specific speeds and packages contact your sales office. DATASHEET DOCUMENT HISTORY 07/10/2000 pg. 1 ...

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