CY2SSTU877 Cypress Semiconductor, CY2SSTU877 Datasheet
CY2SSTU877
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CY2SSTU877 Summary of contents
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... In addition, the CY2SSTU877 features differential feedback clock outputs and inputs. This allows the CY2SSTU877 to be used as a zero delay buffer. When used as a zero delay buffer in nested clock trees, the CY2SSTU877 locks onto the input reference and translates with near zero delay to low-skew outputs. ...
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... Buffered output of input clock, CLK CLK CLK Lz,Y7 Active Lz,Y7 Active Condition CY2SSTU877 Description Outputs Y# FBOUT FBOUT Lz,Y7# Active Lz,Y7# Active Reserved Min ...
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... – – Description Y[0:9], Y#[0:9], FBOUT, FBOUT# CLK, CLK#, FBIN, FBIN# OE (Input Capacitance of CK, CK#, FBIN, FBIN VDDQ or GND Ci(delta) (CK, CK#, FBIN, FBIN VDDQ or GND Description CY2SSTU877 Min. Max. –0.5 V DDQ –0.5 V DDQ –65 150 –0.5 2.5 –50 50 –50 50 –50 50 –100 100 Min ...
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... PRELIMINARY (continued) Description Conditions Above 270 MHz Below 270 MHz Average 1000 cycles (Y[0:9], Y#[0:9] @ 500 MHz any Y/ any Y/Y# Figure 1. Test Loads for Timing Measurement #1 Figure 2. Test Loads for Timing Measurement #2 CY2SSTU877 Min. Max. Unit – – – – ...
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... Document #: 38-07575 Rev. *B PRELIMINARY Figure 3. Cycle to Cycle Jitter Figure 4. Period Jitter Figure 5. Half Period Jitter CY2SSTU877 Page ...
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... Document #: 38-07575 Rev. *B PRELIMINARY Figure 6. Static Phase Offset Figure 7. Dynamic Phase Offset Figure 8. Output Skew CY2SSTU877 Page ...
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... CY2SSTU877BVC-XX CY2SSTU877BVC-XXT CY2SSTU877LFI-XX CY2SSTU877LFI-XXT CY2SSTU877BVI-XX CY2SSTU877BVI-XXT Lead-free CY2SSTU877LFXC-XX CY2SSTU877LFXC-XXT CY2SSTU877BVXC-XX CY2SSTU877BVXC-XXT CY2SSTU877LFXI-XX CY2SSTU877LFXI-XXT CY2SSTU877BVXI-XX CY2SSTU877BVXI-XXT Document #: 38-07575 Rev. *B PRELIMINARY Figure 9. Time Delay Between OE and Clock Output (Y, Y) Figure 10. Input/Output Slew Rates Package Type 40-pin QFN 40-pin QFN – Tape and Reel 52-pin VFBGA 52-pin VFBGA– ...
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... TOP VIEW 4.50±0.10 40-lead QFN LF40A SIDE VIEW 0.08[0.003] 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0°-12° C SEATING PLANE CY2SSTU877 BOTTOM VIEW A1 CORNER Ø0. Ø0. Ø0.30±0.05(52X ...
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... Document History Page Document Title:CY2SSTU877 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Document Number: 38-07575 Rev. ECN No. Issue Date ** 129198 08/22/03 *A 204389 See ECN *B 310414 See ECN Document #: 38-07575 Rev. *B PRELIMINARY Orig. of Change Description of Change RGL New Data Sheet RGL Added more Information. Deleted 4 rows from the bottom of the Pin description ...