CY2PD817 Cypress Semiconductor, CY2PD817 Datasheet

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... The CY2PD817 is a low-voltage LVPECL-to-LVPECL and LVCMOS fanout buffer designed for servers, data communi- cations, and clock management. The CY2PD817 is ideal for applications requiring mixed differ- ential and single-ended clock distribution. This device accepts an LVPECL input reference clock and provides one LVPECL and six LVCMOS/LVTTL output clocks ...

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... Functional Ripple Frequency < 100 kHz Non-functional Functional Functional Functional Functional Manufacturing test CY2PD817 Description LVPECL reference clock input LVPECL reference clock input LVPECL clock output LVPECL clock output Bank A, LVCMOS clock outputs Bank B, LVCMOS clock outputs Clear divider input. See functional Table 1 Output enable/disable input ...

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... BankA to BankB Skew PECL Output to all Banks Skew PCLKI to PCLKO PCLKI to QA/QB PCLKI to PCLKO PCLKI to QA/ any output OE to any output LVPECL output LVTTL output . TT . Parameters are guaranteed by characterization and are not 100% tested. TT CY2PD817 Min. Typ. Max. 250 – V – 1.3 DD 1.0 – V – 0.6 DD – ...

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... Differential ohm Pulse ohm Generator ohm ohm VTT ohm T VTT Figure 1. CY2PD817 Test Reference PECL_CLK V CMR PECL_CLK Q Figure 2. Propagation Delay (TPD) Test Reference Figure 3. Output Duty Cycle Figure 4. Output-Output Skew CY2PD817 ohm ohm ...

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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges Figure 5. Output Enable/Disable Time Package Type 24-pin TSSOP 24-pin TSSOP – Tape and Reel CY2PD817 Product Flow Commercial, 0°C to +85°C 51-85119-** Page ...

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... Document History Page Document Title: CY2PD817 320-MHz 1:7 PECL to PECL/CMOS Buffer Document Number: 38-07574 REV. ECN NO. Issue Date ** 129024 08/29/03 Document #: 38-07574 Rev. ** Orig. of Change RGL New Data Sheet CY2PD817 Description of Change Page ...