CY28378 Cypress Semiconductor, CY28378 Datasheet
CY28378
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CY28378 Summary of contents
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... PCI_F0:2 2 PCI0:6 GND_PCI VDD_48MHz 3V66_3/48MHz_1 VDD_48MHz VDD_PCI 48MHz_0 VTT_PWRGD# RESET# 24_48MHz GND_48MHz 2 *FS0/48MHz_0 *FS1/24_48MHz VDD_48MHz RESET# • 3901 North First Street • CY28378 ® 845 Series Chipset 3V66 PCI REF 48M [ REF0/MULTSEL0 GND_REF VDD_CPU ...
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... Table 2. This output will be used as the reference clock for USB host controller in Intel 845 (Brookdale) platforms. For Intel Brookdale – G platforms, this output will be used as the VCH reference clock. 150k internal pull up. CY28378 Description Page ...
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... Connect to 3.3V. G Ground Connection: Connect all ground pins to the common system ground plane. P 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. G Analog Ground Connection: Ground for core logic, PLL circuitry. CY28378 Description Page ...
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... Output Current I = 4*Iref 6*Iref OH CY28378 PLL Gear Constants (G) 47.99750 47.99750 47.99750 47.99750 47.99750 47.99750 47.99750 47.99750 63.99667 63.99667 63.99667 63.99667 63.99667 63.99667 63.99667 63.99667 63.99667 63.99667 95.99500 95.99500 95.99500 95.99500 95.99500 95.99500 95.99500 47 ...
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... Read = 1 29 Acknowledge from slave 30:37 Byte count from slave – 8 bits 38 Acknowledge 39:46 Data byte from slave – 8 bits 47 Acknowledge 48:55 Data byte from slave – 8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop CY28378 Page ...
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... SW Frequency selection bits. See Table 2. Name (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) CY28378 Byte Read Protocol Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the ...
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... Vendor Test Mode (always program to 0) Name Latched FS[4:0] inputs. These bits are read only Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings 0 = 48-MHz output on pin 27 66-MHz output on pin 24-MHz,1 = 48-MHz CY28378 Pin Description Pin Description Pin Description Pin Description Page ...
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... WD_TIMER time stamp This bit allows setting the Revert Frequency once the system is rebooted 0: Hardware 1: Last Programmed Reserved Watchdog timer time stamp selection: 0000: Off 0001: 1 second 0010: 2 seconds . . . 1110: 14 seconds 1111: 15 seconds Reserved CY28378 Pin Description Pin Description Page ...
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... Set according to Frequency Selection Table 1 = Set according to Fractional Aligner settings PCI skew control 00 = Normal 01 = –500 Reserved 11 = +500 ps 3V66 skew control 00 = Normal 01 = –150 +150 +300 ps Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CY28378 Pin Description Pin Description Pin Description Page ...
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... If the Watchdog times out before the new SMBus reprograms the Watchdog Timer bits to (0000), then this device will send a low system reset pulse, on SRESET# and changes WD Time-out bit to “1.” CY28378 Pin Description Pin Description Pin Description Page ...
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... This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Fixed Value for M-Value Register 48 40 CY28378 SET DIAL-A-FREQUENCY Load M and N Registers Set Pro_Freq_EN = 1 CLEAR W D Exit ...
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... LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low “stopped” state. CY28378 Units pF pF ...
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... PCI clock cycles. Table 9. PWRDWN# Functionality PWRDWN# CPUT 1 Normal 0 Iref x2 Document #: 38-07519 Rev. ** Tstable <1.8ms Tdrive_PWRDN# <300 s, >200mV CPUC 3V66 Normal 66MHz Float Low CY28378 PCI_F/PCI 48MHz 3V66/2 48M Low Low Page ...
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... Configuration REF, 48 MHz Type Type 3V66, PCI Type Type REF, 48MHz Type Type 3V66, PCI, Type Type Three-state CY28378 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD –65 +150 ° °C – 150 ° ...
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... V oh [5] –0.2 [5] 0.65 0.74 [5] 0.0 0.05 [5] 250 550 CY28378 Max. Unit 250 Unit % ps V/ns V/ns ps V/ Page ...
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... Figure 5. Lumped Load For Single-Ended Output Signals (for AC Parameters Measurement) Document #: 38-07519 Rev PCB T PCB Figure 4. 0.7V Configuration CY28378 Measurem ent Point 2pF Measurem ent Point 2pF Page ...
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... Wait for Sample Sels Delay VTT_PWRGD# State 1 State 2 On Figure 6. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 VDDA = off Normal Operation VTT_PWRGD# = toggle CY28378 Device is not affected, VTT_PWRGD# is ignored State 3 On [6] S2 Sample Inputs straps Wait for 1.146ms Enable Outputs Page ...
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... All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock Skew 3V66 3V66 t 5 PCI-PCI Clock Skew PCI PCI t 6 3V66-PCI Clock Skew 3V66 PCI t 7 Document #: 38-07519 Rev CY28378 Page ...
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... Ordering Code CY28378OC 48-pin Small Shrunk Outline Package (SSOP) CY28378OCT 48-pin Small Shrunk Outline Package (SSOP) –Tape and Reel Document #: 38-07519 Rev Package Type CY28378 Operating Range Commercial, 0°C to 70°C Commercial, 0°C to 70°C Page ...
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... Cermaic Caps µ VIA to GND plane layer V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = .1 f ceramic * For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3 CY28378 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-Lead Shrunk Small Outline Package O48 CY28378 51-85061-C Page ...
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... Document History Page Document Title: CY28378 FTG for Pentium 4 Document Number: 38-07519 REV. ECN NO. Issue Date ** 123742 03/06/03 Document #: 38-07519 Rev. ** ® ® and Intel 845 Series Chipset Orig. of Change RGL New Data Sheet CY28378 Description of Change Page ...