CY28346 Cypress Semiconductor, CY28346 Datasheet - Page 5

• Manufacturer Part Number: CY28346
• Description: Clock Synthesizer with Differential CPU Outputs
• Manufacturer: Cypress Semiconductor

Document #: 38-07331 Rev. *B
Byte 6: Silicon Signature Register
Byte 7: Reserved Register
Byte 8: Dial-a-Frequency Control Register N
Byte 9: Dial-a-Frequency Control Register R
Note:
4.
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
@Pup
@Pup
@Pup
@Pup
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
R5, MSB
R4
R3
R2
R1
R0
DAF_ENB
Pin#
Pin#
N6, MSB
N5
N4
N3
N2
N3
N0, LSB
Name
Name
Revision = 0001
Vendor Code = 0011
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
These bits are for programming the PLL’s internal R register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded
from DAF (SMBus) registers.
Reserved. Set = 0.
These bits are for programming the PLL’s internal N register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
[4]
(all bits are Read-only)
Description
Description
Description
Description
CY28346
Page 5 of 20