CY22050 Cypress Semiconductor, CY22050 Datasheet
CY22050
Available stocks
Related parts for CY22050
CY22050 Summary of contents
Page 1
... VDDL 10 LCLK1 LCLK2 LCLK3 8 • 3901 North First Street One-PLL General Purpose Benefits Specifications Field-programmable commercial temperature Field-programmable industrial temperature LCLK1 LCLK2 Output LCLK3 Select Matrix LCLK4 CLK5 CLK6 PWRDWN , • San Jose CA 95134 • Revised January 29, 2005 CY22050 408-943-2600 ...
Page 2
... REF, PLL frequency, output frequencies and/or post-dividers, and different functional options. CyClocksRT Notes: 1. The CY22050 has no internal pull-up or pull-down resistors. PWRDWN and OE pins need to be driven as appropriate or tied to power or ground. 2. Float XOUT if XIN is driven by an external clock source. Document #: 38-07006 Rev. *D Description level (3 ...
Page 3
... PLL-based Systems: Causes, Effects, and Solutions,” available at http://www.cypress.com (click on “Application Notes”), or contact your local Cypress Field Applications Engineer. CY22050 Frequency Calculation The CY22050 is an extremely flexible clock generator with up to six individual outputs, generated from an integrated PLL. REF Q PFD ...
Page 4
... CY22150F for serial configuration and control of the input load capacitors. For an external clock source, the default is 0. Input load capacitors are placed on the CY22050 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply, and temperature changes ...
Page 5
... Defined in Figure 3 DD DDL Output clock fall time, 80% – 20 Defined in Figure 3 DD DDL Output-output skew between related outputs Peak-to-peak period jitter (see Figure 4) for specific output frequency configurations. VDDL CY22050 Min. Typ. Max 0.7 1.0 0 ...
Page 6
... Test Circuit V DD 0.1 µ 0.1 µF CLK Document #: 38-07006 Rev. *D OUTPUTS GND t1 t2 CLK 50% 50% Figure 2. Duty Cycle Definition t2/ 80% CLK 20% Figure 3. Rise and Fall Time Definitions t6 Figure 4. Peak-to-Peak Jitter CY22050 CLK out C LOAD V DDL 0.1 µF Page ...
Page 7
... Parameter θ JA Complexity Note: 9. The CY22050ZC-xxx and CY22050ZI-xxx are factory-programmed configurations. Factory programming is available for high-volume design opportunities of 100 Ku/year or more in production. For more details, contact your local Cypress field application engineer or Cypress sales representative. Document #: 38-07006 Rev. *D Package Type Name ...
Page 8
... Cypress against all charges. 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 6.25[0.246] PACKAGE WEIGHT 0.05gms 6.50[0.256] 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY22050 MAX. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85091-*A Page ...
Page 9
... Document History Page Document Title: CY22050 One-PLL General Purpose Flash-Programmable Clock Generator Document Number: 38-07006 Issue REV. ECN NO. Date ** 108185 08/08/01 *A 110054 03/04/02 *B 121862 12/14/02 *C 310575 See ECN *D 314233 See ECN Document #: 38-07006 Rev. *D Orig. of Change Description of Change CKN New Data Sheet CKN Changed from Preliminary to Final ...