DS90CR213MTD National Semiconductor, DS90CR213MTD Datasheet - Page 5

• Manufacturer Part Number: DS90CR213MTD
• Description: 21-Bit Channel Link66 MHz
• Manufacturer: National Semiconductor

PrintDate=1998/01/07 PrintTime=09:53:21 28561 ds012888 Rev. No. 5 cmserv
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Symbol
Over recommended operating supply and temperature ranges unless otherwise specified
Receiver Switching Characteristics
Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM
AC Timing Diagrams
cable skew (type, length) + source clock jitter (cycle to cycle)
RxCLK OUT Period ( Figure 7 )
RxCLK OUT High Time ( Figure 7 )
RxCLK OUT Low Time ( Figure 7 )
RxOUT Setup to RxCLK OUT ( Figure 7 )
RxOUT Hold to RxCLK OUT ( Figure 7 )
RxCLK IN to RxCLK OUT Delay
Receiver Phase Lock Loop Set ( Figure 11 )
Receiver Powerdown Delay ( Figure 15 )
FIGURE 3. DS90CR214 (Receiver) CMOS/TTL Output Load and Transition Times
FIGURE 2. DS90CR213 (Transmitter) LVDS Output Load and Transition Times
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FIGURE 1. “Worst Case” Test Pattern
@
Parameter
25˚C, V
CC
= 5.0V ( Figure 9 )
(Continued)
5
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
Proof
10.5
Min
4.3
7.0
4.5
2.5
6.5
6.4
15
6
4
Typ
4.2
5.2
T
5
9
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Max
10.7
50
10
1
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Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
5