IDT72V205L15PF IDT, Integrated Device Technology Inc, IDT72V205L15PF Datasheet - Page 2

• Manufacturer Part Number: IDT72V205L15PF
• Description: IC FIFO SYNC 16KX9 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V205L15PF

• Function: Asynchronous
• Memory Size: 144K (16K x 9)
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 4.5Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 256x18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 30mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72V205L15PF

DESCRIPTION (CONTINUED)
PIN CONFIGURATIONS
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
programmable flags is controlled by a simple state machine, and is initiated by
asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO
is used in a single device configuration.
Standard mode and First Word Fall-Through (FWFT) mode.
on the data output lines unless a specific read operation is performed. A read
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
There are two possible timing modes of operation with these devices: IDT
In IDT Standard Mode, the first word written to an empty FIFO will not appear
PIN 1
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
STQFP (PP64-1, order code: TF)
TQFP (PN64-1, order code: PF)
TOP VIEW
2
TM
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word.
First Word Fall Through mode (FWFT). The XI and XO pins are used to expand
the FIFOs. In depth expansion configuration, First Load (FL) is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
IDT’s high-speed submicron CMOS technology.
In FWFT mode, the first word written to an empty FIFO is clocked directly
These devices are depth expandable using a Daisy-Chain technique or
The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
4294 drw 02
Q
Q
GND
Q
Q
V
Q
Q
Q
Q
Q
Q
Q
V
GND
GND
OCTOBER 22, 2008
CC
CC
14
13
12
11
10
9
8
7
6
5
4