IDT72V205L20TF IDT, Integrated Device Technology Inc, IDT72V205L20TF Datasheet - Page 13

• Manufacturer Part Number: IDT72V205L20TF
• Description: IC FIFO SYNC 16KX9 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V205L20TF

• Function: Asynchronous
• Memory Size: 144K (16K x 9)
• Access Time: 20ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 4.5Kb
• Access Time (max): 12ns
• Word Size: 18b
• Organization: 256x18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 50MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 30mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72V205L20TF

NOTES:
1. t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
NOTES:
1. When t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Q
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
D
Q
D
0
0
0
edge of RCLK and the rising edge of WCLK is less than t
Latency Timing apply only at the Empty Boundary (EF = LOW).
0
WCLK
WCLK
SKEW1
RCLK
RCLK
WEN
- D
WEN
- Q
- Q
- D
REN
REN
OE
OE
EF
FF
17
17
17
17
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
SKEW1
t
t
ENS
LOW
LOW
DS
DATA IN OUTPUT REGISTER
minimum specification, t
t
ENS
DATA WRITE 1
t
SKEW1
NO WRITE
t
t
(1)
ENH
SKEW1
DATA IN OUTPUT REGISTER
Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode)
FRL
Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode)
(maximum) = t
t
ENH
t
A
t
FRL
(1)
t
WFF
CLK
SKEW1
t
REF
+ t
, then FF may not change state until the next WCLK edge.
SKEW1.
t
DS
When t
DATA WRITE
SKEW1
t
13
WFF
< minimum specification, t
t
A
TM
t
REF
DATA READ
t
ENS
t
t
ENS
DS
t
FRL
SKEW1
DATA WRITE 2
NO WRITE
(maximum) = either 2 * t
(1)
t
ENH
t
SKEW1
DATA READ
t
ENH
COMMERCIAL AND INDUSTRIAL
t
A
t
FRL
CLK
TEMPERATURE RANGES
t
WFF
(1)
+ t
SKEW1,
NEXT DATA READ
OCTOBER 22, 2008
t
REF
or t
CLK
t
DS
4294 drw 09
+ t
4294 drw 10
SKEW1.
DATA
WRITE
The