IDT72241L25PF IDT, Integrated Device Technology Inc, IDT72241L25PF Datasheet - Page 5

• Manufacturer Part Number: IDT72241L25PF
• Description: IC FIFO 2048X18 SYNC 25NS 32QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72241L25PF

• Function: Synchronous
• Memory Size: 36.8K (2K x 18)
• Data Rate: 40MHz
• Access Time: 25ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72241L25PF

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SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 - D8)
CONTROLS:
RESET (RS)
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full flag (PAF) will be reset
to HIGH after t
flag (PAE) will be reset to LOW after tRSF. During reset, the output register is
initialized to all zeros and the offset registers are initialized to their default values.
WRITE CLOCK (WCLK)
(WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of WCLK. The Full Flag (FF) and Programmable Almost-Full flag
(PAF) are synchronized with respect to the LOW-to-HIGH transition of WCLK.
WRITE ENABLE 1 (WEN1)
is the only enable control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM array on the LOW-
to-HIGH transition of every Write Clock (WCLK). Data is stored in the RAM array
sequentially and independently of any ongoing read operation.
holds the previous data and no new data is allowed to be loaded into the register.
expansion, there are two enable control pins. See Write Enable 2 paragraph
below for operation in this configuration.
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after t
is ignored when the FIFO is full.
READ CLOCK (RCLK)
Clock (RCLK). The Empty Flag (EF) and Programmable Almost-Empty flag
(PAE) are synchronized with respect to the LOW-to-HIGH transition of RCLK.
READ ENABLES (REN1, REN2)
RAM array to the output register on the LOW-to-HIGH transition of the Read
Clock (RCLK).
the previous data and no new data is allowed to be loaded into the register.
go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, the Empty Flag (EF) will go HIGH after t
read can begin. The Read Enables (REN1, REN2) are ignored when the FIFO
is empty.
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
The Write and Read Clocks can be asynchronous or coincident.
If the FIFO is configured for programmable flags, Write Enable 1 (WEN1)
In this configuration, when Write Enable 1 (WEN1) is HIGH, the input register
If the FIFO is configured to have two write enables, which allows for depth
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
The Write and Read Clocks can be asynchronous or coincident.
When both Read Enables (REN1, REN2) are LOW, data is read from the
When either Read Enable (REN1, REN2) is HIGH, the output register holds
When all the data has been read from the FIFO, the Empty Flag (EF) will
Data inputs for 9-bit wide data.
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
RSF
WFF
. The Empty Flag (EF) and Programmable Almost-Empty
, allowing a valid write to begin. Write Enable 1 (WEN1)
REF
and a valid
5
OUTPUT ENABLE (OE)
receive data from the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
WRITE ENABLE 2/LOAD (WEN2/LD)
programmable flags or to have two write enables, which allows depth expansion.
If Write Enable 2/Load (WEN2/LD) is set HIGH at Reset (RS = LOW), this pin
operates as a second write enable pin.
(WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be
loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock (WCLK). Data is stored in the RAM array sequentially and
independently of any ongoing read operation.
Enable 2/Load (WEN2/LD) is LOW, the input register holds the previous data
and no new data is allowed to be loaded into the register.
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after t
and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
2/Load (WEN2/LD) is set LOW at Reset (RS=LOW). The IDT72421/72201/
72211/72221/72231/72241/72251 devices contain four 8-bit offset registers
which can be loaded with data on the inputs, or read on the outputs. See Figure
3 for details of the size of the registers and the default values.
1 (WEN1) and Write Enable 2/Load (WEN2/LD) are set LOW, data on the inputs
D is written into the Empty (Least Significant Bit) Offset register on the first LOW-
to-HIGH transition of the Write Clock (WCLK). Data is written into the Empty (Most
Significant Bit) Offset register on the second LOW-to-HIGH transition of the Write
Clock (WCLK), into the Full (Least Significant Bit) Offset register on the third
transition, and into the Full (Most Significant Bit) Offset register on the fourth
transition. The fifth transition of the Write Clock (WCLK) again writes to the Empty
(Least Significant Bit) Offset register.
or two offset registers can be written and then by bringing the Write Enable 2/
Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write
operation. When the Write Enable 2/Load (WEN2/LD) pin is set LOW, the Write
Enable 1 (WEN1) is LOW, the next offset register in sequence is written.
NOTE:
1. For the purposes of this table, WEN2 = V
2. The same selection sequence applies to reading from the registers. REN1 and REN2
are enabled and read is performed on the LOW-to-HIGH transition of RCLK.
LD
This is a dual-purpose pin. The FIFO is configured at Reset to have
If the FIFO is configured to have two write enables, when Write Enable
In this configuration, when Write Enable (WEN1) is HIGH and/or Write
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
The FIFO is configured to have programmable flags when the Write Enable
If the FIFO is configured to have programmable flags when the Write Enable
However, writing all offset registers does not have to occur at one time. One
0
0
1
1
When Output Enable (OE) is enabled (LOW), the parallel output buffers
WEN1
0
1
0
1
WFF
Figure 2. Write Offset Register
, allowing a valid write to begin. Write Enable 1 (WEN1)
WCLK
IH
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
COMMERCIAL AND INDUSTRIAL
.
TEMPERATURE RANGES
Selection
OCTOBER 22, 2008