IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet
IMP16C552-CJ68
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IMP16C552-CJ68 Summary of contents
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... TXRdy0 VCC RTS0 DTR0 SOUT0 408-432-9100/www.impweb.com IMP16C552 IMP16C552 DMA signaling for transfer of data bi-directional centronics CMOS low power DSR*D INT2 SLIN*+ INIT*+ AFD*+ STB*+ VSS PD0 PD1 PD2 PD3 PD4 PD5 PD6 ...
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... FIFO buffers and host CPU allows single or multiple character transfers. Each UART has a maximum recommended data rate of 256k with a clock frequency of 80MHZ General Description The IMP16C552 is an enhanced dual channel version of the IMP16C550A 2 Asynchronous (UART) plus a bi-directional parallel data port ...
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... IOW* SELECT IOR* AND CLK CONTR OL MR* LOGIC CS0* CS1* CS2* DATA BUS D0-D7 BUFFER FIGURE 2 - IMP16C552 Block Diagram 3 RCVR BUFR INT0 REGISTER UART 0 TXRDY0* SELECT 1 RXRDY0* CONTROL RECEIVER LOGIC FIFO XMIT HOLD REGISTER XMIT FIFO MODEM CONTROL RCVR BUFR REGISTER ...
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... A2,A1, IMP16C552 IMP16C552 description Chip select pins: when CS0,CS1 and CS2 are low the chip is selected this enable communication between the device and the CPU cs0 selects serial channel 0,CS1* selects serial channel 1 and CS2* selects the parallel port Read strobe :when IOR* is low while the chip is selected the CPU can ...
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... VSS 43.54 5 IMP16C552 IMP16C552 description Master reset: When this input is low it clears all the register(except the Receiver Buffer, Transfer Holding and Divisor Latches) and the control logic of the both channels and parallel port the states of various output signals are affected by an active RESET input (refer to table 1) .this input is buffered with a TTL-compatible schmitt trigger with 0 ...
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... BDO OUT 44 6 IMP16C552 IMP16C552 Description Data Terminal Ready :When low this informs the MODEM or data set that the UART is ready to establish a communication link DTR0(1)* output signal can be set to an active low by programming bit 0 (DTR) of the MODEM Control Register to a 1.A Master reset operation sets this inactive (high) state ...
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... LPTOE IMP16C552 IMP16C552 description Serial channel interrupts Tri-state @ output (enable by bits of MCR of each serial channel )goes high whenever an interrupt is pending for the associated serial channel These pins are tri-stated whenever associated channel is in loopback mode. These pins are reset during a Master Reset ...
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... Line Status Register Mode Status Register SOUT INTRPT(RCVR ERRS) INTRPT(RCVR DATA READY) INTRPT(THRE) RTS* DTR* RCVR FIFO 8 IMP16C552 IMP16C552 Reset control Reset state Master Reset All bits low-bits(4-7)are Permanently low Master Reset Bit 0is forced high and bits(1-3),6,7are low-bits permanently Low ...
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... RXRDY° ,TXRDY° Parallel port Port data register Port status register Port control register STB°AFD°INIT°SLIN INT2 9 IMP16C552 IMP16C552 Reset control Reset state Master Reset Undefined data Master Reset All bits low-{(0-3),6,7forced and 4,5 permanent} Master Reset/internal High ...
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... INTERALL REGISTER DESCRIPTION The system programmer has access to any of the register as summerized in Table II Table II Accessible IMP16c552 Registers for each serial channel 0DLAB=0 0DLAB=0 Bit Receiver Transmitter no Buffer Holding Register Register (Read only) RBR THR 0 Data Bit 0 Data Bit0 1 Data Bit 1 Data Bit 1 ...
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... Interrupt (BI Transmitter Holding Register Empty (THRE Transmitter Empty (TEMT Error in RCVR FIFO(``) (EIRF) (*) These bits are read 0 in Character Mode of IMP16C552 11 IMP16C552 IMP16C552 Register address 6 7 0DLAB=1 MODEM Scratch Divisor Status Pad Latch Register Register (LSB) MSR SCR ...
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... IMP16C552 IMP16C552 Bit 6:thus bit is the break control bit it causes a break control condition to be transmitted to the receiving UART when bit 6 set to a logic 1 the serial output (SOUT) is forced to the ...
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... Percent Error Difference Between Desired and Actual 3840 - 2560 - 1745 0.026 1428 0.034 1280 - 640 - 320 - 160 - 107 0.312 0.628 1.230 14.285 408-432-9100/www.impweb.com IMP16C552 IMP16C552 © 2002 IMP, Inc. ...
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... Stop bit following the last data bit or parity bit is detected as a logic 0 bit (Spacing level). The FE indicator is reset whenever the CPU reads the contents of the Line Status Register. In the FIFO mode 408-432-9100/www.impweb.com IMP16C552 IMP16C552 © 2002 IMP, Inc. ...
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... Table VI) Bit3 : In the character mode this bit 0 in the FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending Bit 4,5: These two bits of the IIR are always logic 0 408-432-9100/www.impweb.com IMP16C552 IMP16C552 to provide minimum software The four levels of ...
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... Empty Empty Fourth MODEM Clear to send or Status Data Set ready or Ring Indicator or Received Line Signal Detect 408-432-9100/www.impweb.com IMP16C552 IMP16C552 Interrupt reset control .--- Reading the Line Status Register Reading the Receiver Buffer Register or the FIFO Drops below the Trigger Level Reading the ...
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... Status Interrupt when set to logic 1. Bit 3: This bit enables the MODEM Status Interrupt when set to logic 1. 17 IMP16C552 IMP16C552 Bit 4-7: These four bits are always logic 0. Scratch Pad Register This 8-bit Read/Write Register does not control the UART in anyway intended as ...
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... CPU. Bit 1: This bit is the Delta Data Set Ready (DDSR) indicator, Bit 1 when set to logic 1, indicates that the DSR input to the chip has 408-432-9100/www.impweb.com IMP16C552 IMP16C552 (high) state: the receiver Serial © 2002 IMP, Inc. ...
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... CPU reads one character form the RCVR FIFO. D. When a occurred the ` timeout timer is reset after programmed a new character is received or after the 408-432-9100/www.impweb.com IMP16C552 IMP16C552 line status interrupt timeout interrupt has not © 2002 IMP, Inc. ...
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... LSR7 will indicate whether there are any errors in the RCVR FIFO. There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode. However, the RCVR and XMIT FIFO’s are still fully capable of holding characters. 408-432-9100/www.impweb.com IMP16C552 XMITTER are controlled © 2002 IMP, Inc. ...
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... CPU to write data to the parallel port. Bits 0-7: Data bits Port Status Register This register is a read only register reporting the state of status input pins ERROR*, SLCT, PE, ACK*, and BUSY. 21 IMP16C552 IMP16C552 LOW* Operation 1 Read Port Data Register 1 Read Port Status Register 1 ...
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... Avg. Power Supply Current(Vcc) IIL Input Leakage ICL Clock Leakage LOZ Tri-State® Leakage VILMR MR Schmitt VIL VIHMR MR Schmitt VIH 22 IMP16C552 IMP16C552 If Military/Aerospace specified devices are required. contact Modular for availability and +70 c specifications. 0 – indicate limits damage may occur. Continuous operation at these limits is not intended and should be -0 ...
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... Fc =1 MHz Output Unmeasured pins Returned to VSS t XH 2.4V 2.0V Note:1 0.8V 0. Reset Timing t MR FIGURE 4 – Clock and Reset Timing Min 408-432-9100/www.impweb.com IMP16C552 IMP16C552 Min Typ Max Units Test Points 2.0V Note:2 0.8V Max Units Test Conditions ...
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... CYCLES LW FIGURE 5 – Baud Rate General Timing Min Max Units -1) 125 nsec 125 nsec 75 nsec 100 nsec 408-432-9100/www.impweb.com IMP16C552 IMP16C552 (n-2)XTAL1 CYCLES HW ss Test Conditions 100pF Load 100pF Load 100pF Load (fx=8. 0 MHz+2) 100pF Load (fx=8. 0 MHz+2) ...
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... A0,A1,A2 CS0*(CS1*) IOW* IOR* DATA D0-D7 A0,A1,A2 CS0*(CS1*) IOR* IOW* BD0 DATA D0-D7 25 IMP16C552 IMP16C552 VALID t t ACW t DOC t t DOC DOW ACTIVE t DH tDD VALID DATA FIGURE 6 – Write cycle Timing VALID t ACR t DIC t t DIC t DIW ACTIVE DDD ...
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... IOW* delay from chip Select or Address tACR Address and Chip Select Hold time from IOR* tACW Address and Chip Select Hold time from IOW* tWC Write Cycle Delay tRC Read Cycle Delay 26 IMP16C552 IMP16C552 Min Max Units nsec 50 105 nsec 0 60 nsec 40 nsec ...
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... Read cycle Timing Symbol Parameter tMDO Delay from IOW* (WR MCR) tSIM Delay to Set Interrupt From MODEM Input tRIM Delay to Reset Interrupt From IOR* (RD MSR) 27 IMP16C552 IMP16C552 t MDO t t SIM SIM t t RIM RIM FIGURE 8 – Modem Control Timing Min Max ...
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... TrinT Delay From IOR* (RD RBR or RD LSR) Reset Interrupt (*) When receiving the first byte in FIFO mode tSINT will be delayed 3 RCLK cycles, except for a timeout interrupt where tSINT will be delayed 8 RCLK cycles. 28 IMP16C552 IMP16C552 t SCD 8 CLKS PARITY START START DATA BITS(5-8) STOP ...
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... FIGURE 10 – RCVR FIFO Timing for First Byte PARITY START DATA(5-8) STOP t SINT top byte of FIFO t SINT ACTIVE previous byte read from FIFO 408-432-9100/www.impweb.com IMP16C552 IMP16C552 t t SINT RINT FIFO below trigger level t RINT ACTIVE ACTIVE FIFO at or above trigger level t RINT FIFO below trigger levle ...
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... FIGURE 12 – Receiver DMA Timing (FCR0=0 or FCR0=1 and FCR3=0) IOR* (read RBR) SIN0 (first byte that reaches trigger level) SAMPLE CLK RXRDY* Note 1 Reading of last byte from FIFO FIGURE 13 – Receiver DMA Timing (FCR0=1 and FCR3=1) 30 IMP16C552 IMP16C552 ACTIVE Note1 STOP PARITY t SINT Mode 0 ACTIVE Note1 STOP PARITY t ...
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... FIGURE 14 – Transmitter Timing Min Max 50 250 408-432-9100/www.impweb.com IMP16C552 IMP16C552 START tSTI tIR Units Test Conditions nsec 100pF Load nsec 100pF Load BAUDOUT Cycles BAUDOUT (note 1) Cycles BAUDOUT (note 1) Cycles (note 1) BAUDOUT 100pF Load ...
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... FCR0=1 and FCR3=0) Mode 0 BYTE#16 PARITY DATA FIFO not full FIFO full tWXI FIGURE 16-Transmitter Ready Timing in DMA (FCR0=0 or FCR0=1 and FCR3=0) Mode 1 408-432-9100/www.impweb.com IMP16C552 IMP16C552 START STOP empty tSXA START STOP FIFO not full tSXA © 2002 IMP, Inc. ...
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... CS2* LPTOE* A0,A1 D0-D7 IOW* IOR* PD0-PD7 SLIN*,INIT* AFD*,STB* IOW* IOR* D0-D7 ACK* INT2 RESET* PD0-PD7 SLIN*,INIT* AFD*,STB* 33 IMP16C552 IMP16C552 ADDRESS 2 Write Data Read Data FIGURE 17- Parallel Port Timing 408-432-9100/www.impweb.com © 2002 IMP, Inc. ...
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... IOR* low to data valid 12 IOR* high to D7-D0. Hi-Z 13 ACK* to INT2 14 IOW* high to INT2 Hi-Z 15 RST* low to D7-D0, SLIN*, STB* INIT*, AFD* 16 LPTOE* low to PD0-PD7 Delay 17 LPTOE* high to PD0-PD7Hi-Z ORDERING INFORMATION Part Number IMP16C552-CJ68 IMP16C552-IJ68 34 IMP16C552 IMP16C552 Min Max Units 100 ns 100 ...