LMX2433TM National Semiconductor, LMX2433TM Datasheet - Page 30

• Manufacturer Part Number: LMX2433TM
• Description: PLLatinum Dual High Frequency Synthesizer for RF Personal Communications
• Manufacturer: National Semiconductor

www.national.com
LMX243x FinRF Sensitivity Test Setup
The block diagram above illustrates the setup required to
measure the LMX243x device’s RF input sensitivity level.
The same setup is used for the LMX2430TM Evaluation
Board. The purpose of this test is to measure the acceptable
signal level to the FinRF input of the PLL chip. Outside the
acceptable signal range, the feedback divider begins to di-
vide incorrectly and miscount the frequency. The FinIF sen-
sitivity is evaluated in the same way.
The setup uses an open loop configuration. A power supply
is connected to Vcc. The IF PLL is powered down (IF_PD bit
to the FinRF pin. The 3 dB pad provides a 50Ω match
between the PLL and the signal generator. The EN, ENosc,
and OSCin pins are all tied to Vcc. The N value is typically
set to 10000 in CodeLoader, i.e. RF_B word = 156 and
RF_A word = 16 for RF_P bit = 0 (LMX2434) or RF_P bit =
1 (LMX2430 and LMX2433). The feedback divider output is
routed to the Ftest/LD pin by selecting the RF_N/2 Fre-
quency word (MUX[3:0] word = 15) in CodeLoader. A Uni-
versal Counter is connected to the Ftest/LD pin and used to
monitor the output frequency of the feedback divider. The
= 1). By means of a signal generator, an RF signal is applied
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expected frequency should be the signal generator fre-
quency divided by twice the corresponding counter value,
i.e. 20000. The factor of two comes in because the LMX43x
device has an internal /2 circuit which is used to provide a
50% duty cycle.
Sensitivity is typically measured over frequency, supply volt-
age and temperature. In order to perform the measurement,
the temperature, frequency, and supply voltage is set to a
fixed value and the power level of the signal at FinRF is
varied. Sensitivity is reached when the frequency error of the
divided RF input is greater than or equal to 1 Hz. The power
attenuation from the cable and the 3 dB pad must be ac-
counted for. The feedback divider will actually miscount if too
much or too little power is applied to the FinRF input. There-
fore, the allowed input power level will be bounded by the
upper and lower sensitivity limits. In a typical application, if
the power level to the FinRF input approaches the sensitivity
limits, this can introduce spurs or cause degradation to the
phase noise. When the power level gets even closer to these
limits, or exceeds it, then the RF PLL loses lock.
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