IDT72V205L15TF IDT, Integrated Device Technology Inc, IDT72V205L15TF Datasheet - Page 3

• Manufacturer Part Number: IDT72V205L15TF
• Description: IC FIFO SYNC 16KX9 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V205L15TF

• Function: Asynchronous
• Memory Size: 144K (16K x 9)
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72V205L15TF; 800-1510

PIN DESCRIPTION
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Symbol
D0–D17
RS
WCLK
WEN
RCLK
REN
OE
LD
FL
WXI
RXI
FF/IR
EF/OR
PAE
PAF
WXO/HF
RXO
Q0–Q17
V
GND
CC
Data Inputs
Reset
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Load
First Load
Write Expansion
Input
Read Expansion
Input
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Write Expansion
Out/Half-Full Flag
Read Expansion
Out
Data Outputs
Power
Ground
Name
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I/O
reset is 31 from full for IDT72V205, 63 from full for IDT72V215, and 127 from full for IDT72V225/72V235/72V245.
Data inputs for an 18-bit bus.
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.
When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH,
the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW.
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW.
In the single device or width expansion configuration, FL together with WXI and RXI determine if the mode is
IDT Standard mode or First Word Fall Through (FWFT) mode, as well as whether the PAE/PAF flags are
synchronous or asynchronous. (See Table 1.) In the Daisy Chain Depth Expansion configuration, FL is
grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
In the single device or width expansion configuration, WXI together with FL and RXI determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration, WXI is connected to WXO (Write Expansion
Out) of the previous device.
In the single device or width expansion configuration, RXI together with FL and WXI, determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration, RXI is connected to RXO (Read Expansion
Out) of the previous device.
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In
the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to
the FIFO memory.
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.
When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
offset at reset is 31 from empty for IDT72V205, 63 from empty for IDT72V215, and 127 from empty for IDT72V225/
72V235/72V245.
When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset at
In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the
depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the
FIFO is written.
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last
location in the FIFO is read.
Data outputs for an 18-bit bus.
+3.3V power supply pins.
Seven ground pins.
3
TM
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008