DM74S163N Fairchild Semiconductor, DM74S163N Datasheet
DM74S163N
Specifications of DM74S163N
74S163N
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DM74S163N Summary of contents
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... Ordering Code: Order Number Package Number DM74S161N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74S163N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without addi- tional gating ...
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Logic Diagram www.fairchildsemi.com DM74S161 • DM74S163 2 ...
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Timing Diagram Sequence: 1. Clear outputs to zero 2. Preset to binary twelve 3. Count to thirteen, fourteen, fifteen, zero, one and two 4. Inhibit 3 www.fairchildsemi.com ...
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Parameter Measurement Information Note A:The input pulses are supplied by generators having the following characteristics: PRR 1 MHz, duty cycle 50 For DM74S161/163, t OUT Note B: Outputs Q and carry are tested for ...
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Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...
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Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter V Input Clamp Voltage HIGH Level V OH Output Voltage V V LOW Level V OL Output Voltage V I Input Current @ Max ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...