MCP3301-CI/SL Microchip Technology, MCP3301-CI/SL Datasheet - Page 16

• Manufacturer Part Number: MCP3301-CI/SL
• Description: 13-BIT ADC, DIFF INPUTS, SINGLE CHANNEL, -40C to +85C, 14-SOIC 150mil, TUBE
• Manufacturer: Microchip Technology

MCP3301
6.0
6.1
The MCP3301 A/D converter employs a conventional
SAR architecture. With this architecture, the potential
between the IN+ and IN- inputs are simultaneously
sampled and stored with the internal sample circuits for
1.5 clock cycles (t
input hold switches of the converter open and the
device uses the collected charge to produce a serial
13-bit binary two’s complement output code. This con-
version process is driven by the external clock and
must include 13 clock cycles, one for each bit. During
this process, the most significant bit (MSB) is output
first. This bit is the sign bit and indicates if the IN+ or IN-
input is at a higher potential.
FIGURE 6-1:
DS21700C-page 16
IN+
IN-
Hold
Hold
APPLICATIONS INFORMATION
Conversion Description
C
C
ACQ
SAMP
SAMP
). Following this sample time, the
Simplified Block Diagram.
+
-
Comp
CDAC
D
13-Bit SAR
Register
OUT
Shift
6.2
The analog input of the MCP3301 is easily driven either
differentially or single-ended. Any signal that is com-
mon to the two input channels will be rejected by the
common mode rejection of the device. During the
charging time of the sample capacitor, a small charging
current will be required. For low source impedances,
this input can be driven directly. For larger source
impedances, a larger acquisition time will be required
due to the RC time constant that includes the source
impedance. For the A/D Converter to meet specifica-
tion, the charge holding capacitor (C
given enough time to acquire a 13-bit accurate voltage
level during the 1.5 clock cycle acquisition period.
An analog input model is shown in Figure 6-3. This
model is accurate for an analog input, regardless if it is
configured as a single-ended input or the IN+ and IN-
input in differential mode. In this diagram, it is shown
that the source impedance (R
sampling switch (R
time that is required to charge the capacitor (C
Consequently, a larger source impedance with no addi-
tional acquisition time increases the offset, gain and
integral linearity errors of the conversion. To overcome
this, a slower clock speed can be used to allow for the
longer charging time. Figure 6-2 shows the maximum
clock speed associated with source impedances.
FIGURE 6-2:
vs. Source Resistance (R
INL.
1.8
1.6
1.4
1.2
0.8
0.6
0.4
0.2
1
0
100
Driving the Analog Input
SS
Input Resistance (ohms)
1000
) impedance, directly affecting the
Maximum Clock Frequency
© 2007 Microchip Technology Inc.
SS
) to maintain ±1 LSB
S
) adds to the internal
10000
SAMPLE
) must be
SAMPLE
100000
).