MCP2515-E/PRB2 Microchip Technology, MCP2515-E/PRB2 Datasheet - Page 6

• Manufacturer Part Number: MCP2515-E/PRB2
• Description: CAN controller with SPI interface, 125 deg C, -40C to +125C, 18-PDIP, TUBE
• Manufacturer: Microchip Technology

MCP2515
1.5
The CAN protocol engine combines several functional
blocks, shown in
1.5.1
The heart of the engine is the Finite State Machine
(FSM). The FSM is a sequencer that controls the
sequential data stream between the TX/RX shift
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
the parallel data stream between the TX/RX shift
registers and the buffers. The FSM ensures that the
processes of reception, arbitration, transmission and
error-signaling are performed according to the CAN
protocol. The automatic retransmission of messages
on the bus line is also handled by the FSM.
1.5.2
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code, which is
transmitted after either the Control Field (for messages
with 0 data bytes) or the Data Field and is used to
check the CRC field of incoming messages.
FIGURE 1-4:
DS21801E-page 6
RX
CAN Protocol Engine
PROTOCOL FINITE STATE
MACHINE
CYCLIC REDUNDANCY CHECK
Sample<2:0>
Figure 1-4
Decision
Majority
Receive<7:0>
RecData<7:0>
CAN PROTOCOL ENGINE BLOCK DIAGRAM
BusMon
and described below.
Interface to Standard Buffer
Bit Timing Logic
CRC<14:0>
Comparator
SAM
(Transmit<5:0>, Receive<7:0>)
TrmData<7:0>
Transmit<7:0>
StuffReg<5:0>
Comparator
Shift<14:0>
1.5.3
The Error Management Logic (EML) is responsible for
the fault confinement of the CAN device. Its two
counters, the Receive Error Counter (REC) and the
Transmit Error Counter (TEC), are incremented and
decremented by commands from the bit stream
processor. Based on the values of the error counters,
the CAN controller is set into the states error-active,
error-passive or bus-off.
1.5.4
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus-related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive-
to-dominant bus transition at Start-of-Frame (hard syn-
chronization) and on any further recessive-to-dominant
bus line transition if the CAN controller itself does not
transmit a dominant bit (resynchronization). The BTL
also provides programmable time segments to
compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. The programming of the BTL
depends on the baud rate and external physical delay
times.
ERROR MANAGEMENT LOGIC
BIT TIMING LOGIC
Transmit Logic
Error Counter
Error Counter
Rec/Trm Addr.
Transmit
Protocol
Receive
© 2007 Microchip Technology Inc.
FSM
TX
ErrPas
BusOff
SOF
REC
TEC