SI5326 Silicon Laboratories, SI5326 Datasheet
SI5326
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SI5326 Summary of contents
Page 1
... VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. ...
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... Si5326 Table 1. Performance Specifications (V = 1.8, 2.5, or 3.3 V ±10 – º Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, CKIN2) Output Clock Frequency CK OF (CKOUT1, CKOUT2) Input Clocks (CKIN1, CKIN2) Differential Voltage Swing CKN ...
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... MHz offset — Phase Noise @ 100 kHz Off- — set Max spur @ — (n > < 100 MHz) Still Air — Symbol DIG T JCT T STG Confidential Rev. 0.2 Si5326 Typ Max Unit — 0.3 TBD ps rms 0.3 TBD ps rms TBD TBD ps rms 0.05 0.1 dB TBD ...
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... Si5326 0 -20 -40 -60 -80 -100 -120 -140 -160 100 1000 4 155.52 MHz in, 622.08 MHz out 10000 100000 1000000 Offset Frequency (Hz) Typical Phase Noise Plot Figure 1. Confidential Rev. 0.2 10000000 100000000 ...
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... Figure 2. Si5326 Typical Application Circuit (I Figure 3. Si5326 Typical Application Circuit (SPI Control Mode) Confidential Rev. 0.2 Si5326 2 C Control Mode) 5 ...
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... The device provides virtually any frequency translation combination across this operating range. Independent dividers are available for each input clock and output clock, so the Si5326 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. The Si5326 input clock frequency ...
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... Pin numbers are preliminary and subject to change. Pin # Pin Name I/O Signal Level 1 I LVCMOS RST 2, 9, 14, NC — 30 INT_C1B O LVCMOS Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map RST 1 27 SDI ...
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... I 13 CKIN2– 18 LOL O LVCMOS Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map. 8 CKIN2 Invalid Indicator. This pin functions as a LOS (and optionally FOS) alarm indicator for CKIN2 if CK2_BAD_PIN = CKIN2 present LOS (FOS) on CKIN2. The active polarity can be changed by CK_BAD_POL. If CK2_BAD_PIN = 0, the pin tristates ...
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... CS_CA I/O LVCMOS 22 SCL I LVCMOS Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map. Description Latency Decrement. A pulse on this pin decreases the input to output device latency by 1/f (approximately 200 ps). There is no limit on the range of OSC latency adjustment by this method. ...
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... CMODE I LVCMOS GND PAD GND GND Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map. 10 Serial Data control mode (CMODE = 0), this pin functions as the bidirec- tional serial data port. In SPI control mode (CMODE = 1), this pin functions as the serial data output ...
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... MHz 1.213–1.417 GHz Si5326B-B-GM 2 kHz–808 MHz Si5326C-B-GM 2 kHz–346 MHz Package Range 36-Lead QFN 36-Lead QFN 36-Lead QFN Confidential Rev. 0.2 Si5326 Temperature Range – °C – °C – °C 11 ...
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... Si5326 4. Package Outline: 36-Pin QFN Figure 4 illustrates the package details for the Si5326. Table 3 lists the values for the dimensions shown in the illustration. Figure 4. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 A1 0.00 0.01 b 0.18 0.23 D 6.00 BSC D2 3.95 4.10 e 0.50 BSC E 6.00 BSC E2 3.95 4.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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... Recommended PCB Layout Figure 5. PCB Land Pattern Diagram Confidential Rev. 0.2 Si5326 13 ...
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... Si5326 Table 4. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
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... Added Figure 1, “Typical Phase Noise Plot,” on page 4. Updated Figure 2, “Si5326 Typical Application 2 Circuit (I C Control Mode),” and Figure 3, “Si5326 Typical Application Circuit (SPI Control Mode),” on page 5 to show preferred external reference interface. Updated “2. Pin Descriptions: Si5326”. ...
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... Si5326 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...