SM5904BF Nippon Precision Circuits Inc, SM5904BF Datasheet - Page 24

• Manufacturer Part Number: SM5904BF
• Description: compression and non compression type shock-proof memory controller
• Manufacturer: Nippon Precision Circuits Inc

YFLAG, YFCLK, FLAG6
Correct data demodulation becomes impossible for
the CD signal processor IC when a disturbance
exceeding the RAM jitter margin occurs. The
YFLAG signal input pin is used to indicate when
such a condition has occurred.
The YFCLK is a 7.35 kHz clock synchronized to the
CD format frame 1.
The IC checks the YFLAG input and stops the
1
2
3
4
85H command
YFLGS
0
1
YFCKP
0
1
0
1
When YFLAG=HIGH
When YFLAG=LOW
When YFLAG=LOW on YFCLK input falling edge
When YFLAG=LOW on YFCLK input rising edge
Table 1. YFLAG signal check method
FLAG6 set conditions
SM5904BF
YFCLK be tied either High or Low
encode sequence when such a disturbance has
occurred, and then makes FLAG6 active.
The YFLAG check method used changes depend-
ing on the YFLGS flag and YFCKP flag (85H com-
mand). See table1.
If YFLAGS is set to 1, then YFCLK should be tied
either High or Low.
NIPPON PRECISION CIRCUITS-24
- By status read (90H command)
FLAG6 reset conditions
- When MSON=LOW
- After system reset