SL2101 Zarlink Semiconductor Inc, SL2101 Datasheet
SL2101
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SL2101 Summary of contents
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... SL2101C/KG/LH2N MLP* SL2101C/KG/LH2Q MLP* All codes baked and drypacked Description The SL2101 is a fully integrated single chip broadband mixer oscillator with low phase noise PLL frequency synthesizer intended for use in double conversion tuners as both the up and down converter and is compatible with HIIF frequencies ...
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... SL2101 1 28 XTAL CAP PUMP 2 27 DRIVE XTAL 26 SDA 3 PORT P0 25 SCL 4 Vee 5 24 BUFREF ADD 23 Vccd 6 Vee 22 Vee 7 VccLO 21 Vee 8 LOB RFB VccLO 10 Vee 18 Vee 11 VccRF 17 12 VccLO Vee 16 13 Vee IFOUTPUTB 15 14 IFOUTPUT Figure 2 - Pin Diagram SSOP Package ...
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... The SL2101 is a single chip solution containing all necessary active circuitry and simply requires an external tuneable resonant network for the local oscillator sustaining network. The pin assignment is contained in Figures 2 and 3 for the SSOP and MLP packages and the block diagram in Figure 1 ...
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... The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to SL2101 4 Zarlink Semiconductor Inc. ...
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... Typical applications for the crystal oscillator are contained in Figure 24 and Figure 25. Figure 25 is used when driving a second SL2101 as a downconverter. The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the oscillator ...
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... Buffered crystal reference output, BUFREFThe buffered crystal reference frequency can be switched to the 15 SL2101 14 Figure 4 - Nominal Output Load as Upconverter into Differential SAWF SL2101 Function as described above Function as described above. The charge pump current can be programmed by bits C1 & C0 within data byte 4, as defined in Figure 29. ...
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... Figure 5 - Nominal Output Load as Downconverter, 44 MHz IF SL2101 Figure 6 - Output Load as Downconverter to a Differential Amplifier default setting on SL2101 SL2101 Vcc 820 820 Vcc 15 680 nH 100 nF 680 Supply Current Typ ...
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... Figure Input Impedance Matching Network 860 MHz Upconverter SL2101 27 Jul 2001 11:24:54 1_: 4.3164 -99.426 1.6007 pF 1 000.000 000 MHz 2_: 3.7266 -80.117 1.15 GHz 3_: 4.1328 -70.223 1.25 GHz 4_: 4.7617 -58.166 STOP 1 400.000 000 MHz 100nF 9 RFINPUT 10 200 Ω RFINPUTB 100nF 47nH SL2101 8 Zarlink Semiconductor Inc. Data Sheet 1.4 GHz ...
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... Figure Input Impedance Matching Network as 1.22 GHz Downconverter SL2101 27 Jul 2001 09:05:31 1_: 20.07 -46.965 3.3888 pF 1 000.000 000 MHz 2_: 19.795 3_: 20.666 4_: 25.772 STOP 1 400.000 000 MHz setting) 2.7pF 9 10 10nF 3.9nH 9 Zarlink Semiconductor Inc. Data Sheet -34.527 1.15 GHz -26.233 1.25 GHz -15.155 1.4 GHz RFINPUT RFINPUTB SL2101 ...
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... Figure 12 - Two Tone Intermodulation Test Condition Spectrum, Input Referred 100 200 Figure 13 - Input NF, Typical (Maximum Power Setting) SL2101 df f1- f2+df 300 400 500 600 700 Input frequency (MHz) 10 Zarlink Semiconductor Inc. Data Sheet 800 900 ...
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... Figure 15 - Upconverter Gain, NF and Intermodulation with Recommended Load Versus Power * Measured with 128 channels at +7 dBmV 3x0.5 mm Figure 16 - Upconverter Oscillator Application SL2101 Gain 300 400 500 600 Input frequency(in MHz) typ Typ NF Gain CSO* (dB) (dB) (dBc) 6 ...
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... Figure 18 - Downconverter Oscillator Application 100 1040 1060 1080 1100 Figure 19 - Typical Phase Noise Performance as Downconverter at 10 kHz Offset SL2101 PN 400 500 600 1 kΩ Varactor line 1120 1140 1160 1180 LO frequency 12 Zarlink Semiconductor Inc. Data Sheet 700 ...
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... Figure 20 - Downconverter Gain, NF and IP3 with Recommended (Fig. 4) Load Versus Power CH1 DB1 4.7V PRm Cor Z 0 Avg 50 16 Smo START 1 000.000 000 MHz Figure 21 - Typical IF Output Impedance as Upconverter, Single-Ended SL2101 Typ NF I0 Gain (dB) (dB) 0 10.3 15.6 1 9.3 15.1 0 8.8 14.0 1 8.7 12.1 0 11.6 15 ...
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... SL2101 CH1 1_: 1.3588 k UA6 4.7V PRm Cor Z 0 Avg 50 16 Smo START 10.000 000 MHz Figure 22 - Typical IF Output Impedance as Downconverter, Single-Ended ...
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... SL2101 Figure 23 - Reference Division Ratios 1 47pf 2 47pf ...
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... Figure 25 - Application When Driving Two SL2101 from One Crystal Figure 26 - Test Modes * clocks need to be present on crystal and local oscillator to enable charge pump test modes and to toggle status byte bit FL ...
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... Buffered crystal reference output enable (see Figure port output state POR : Power on reset indicator FL : Phase lock flag MA1 MA0 Table 3 - Address Selection Figure 28 - Read/Write Data Formats Zarlink Semiconductor Inc. SL2101 LSB 0 0 MA1 MA0 ...
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... Composite peak input 9, 10 signal All synthesizer related 14, 15 spurs on IF Output Upconverter application Input frequency range 9, 10 Input impedance Input return loss Input Noise Figure Conversion gain SL2101 Current Min. Typ. 0 +-98 +-130 1 +-210 +-280 0 +-450 +-600 1 +-975 ...
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... LO phase noise, SSB @ 10 kHz offset @ 100 kHz offset LO phase noise floor IF output frequency 14, 15 range IF output impedance Downconverter application Input frequency range 9, 10 Input impedance Input return loss Input Noise Figure SL2101 Min. Typ. Max. Units - 0.5 dB -20 dB -65 dBc -68 dBc ...
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... Input high voltage Input low voltage Input high current Input low current Leakage current Hysterysis SDA output voltage 3 SCL clock rate 4 Charge pump output 28 current Charge pump output 28 leakage SL2101 Min. Typ. Max. Units 12 dB 0 µ V 117 -46 dBc 1 2.3 ...
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... To maximise phase noise the tuning range should be minimised and Q of resonator maximised. The application as in Figure 18 has a tuning range of 200 MHz. Note 5: If the BUFREF output is not used it should be left open circuit or connected to Vccd and disabled by setting RE = '0'. SL2101 Min. Typ. Max. ...
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... All I/O port DC offsets SDA, SCL DC offsets Storage temperature Junction temperature Package thermal resistance, chip to case (SSOP) Package thermal resistance, chip to ambient (SSOP) Power consumption at 5.25 V ESD protection (pins 3-28) ESD protections (pins 1, 2) SL2101 Pin Min. Max. Units 6, 12, -0.3 6 17, 19 ...
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... SL2101 RF inputs IF outputs Figure 30 - Input and Output Interface Circuits (RF section) 23 Zarlink Semiconductor Inc. Data Sheet Oscillator inputs ...
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... V ccd 1 200µA Reference oscillator V ccd * * On SDA only SDA/SCL (pins 3 and 4) P0 Output port Figure 31 - Input and Output Interface Circuits (PLL section) Zarlink Semiconductor Inc. SL2101 Loop amplifier 120K ADD input V ccd 1mA BUFREF output 24 Data Sheet ...
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