MC100EP32DTG ON Semiconductor, MC100EP32DTG Datasheet - Page 2

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MC100EP32DTG

Manufacturer Part Number
MC100EP32DTG
Description
IC DIVIDER DIV X2 ECL CLK 8TSSOP
Manufacturer
ON Semiconductor
Series
100EPr
Datasheet

Specifications of MC100EP32DTG

Logic Type
Divide-by-2
Number Of Elements
1
Number Of Bits Per Element
1
Reset
Asynchronous
Count Rate
4GHz
Trigger Type
Positive, Negative
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Direction
-
Timing
-
Other names
MC100EP32DTGOS
RESET
Figure 1. 8−Lead Pinout (Top View) and Logic
CLK
CLK
V
BB
1
2
3
4
RESET
Table 3. ATTRIBUTES
1. For additional information, see Application Note AND8003/D.
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
CLK
Q
Diagram
B2
R
Characteristics
8
7
6
5
Figure 2. Timing Diagram
V
Q
Q
V
CC
EE
http://onsemi.com
Oxygen Index: 28 to 34
Charged Device Model
Human Body Model
Machine Model
2
TSSOP−8
t
Table 1. PIN DESCRIPTION
*Pins will default LOW when left open.
Table 2. TRUTH TABLE
RR
CLK, CLK*
Reset*
V
Q, Q
V
V
EP
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 2 Function
SOIC−8
BB
CC
EE
CLK
X
Z
DFN8
Pin
CLK
Pb Pkg
Level 1
Level 1
Level 1
X
Z
UL 94 V−0 @ 0.125 in
78 Devices
ECL Clock Inputs
ECL Asynchronous Reset
Reference Voltage Output
ECL Data Outputs
Positive Supply
Negative Supply
(DFN8 only) Thermal exposed pad must
be connected to a sufficient thermal con-
duit. Electrically connect to the most neg-
ative supply (GND) or leave unconnec-
ted, floating open.
> 200 V
> 4 kV
> 2 kV
Value
75 kW
N/A
RESET
Pb−Free Pkg
Z
L
Level 1
Level 3
Level 1
Function
Q
F
L
Q
H
F

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