HEF4020BP,652 NXP Semiconductors, HEF4020BP,652 Datasheet
HEF4020BP,652
Specifications of HEF4020BP,652
933282710652
HEF4020BPN
Related parts for HEF4020BP,652
HEF4020BP,652 Summary of contents
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HEF4020B 14-stage binary counter Rev. 06 — 27 November 2009 1. General description The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 ...
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... NXP Semiconductors 5. Functional diagram CP MR Fig 1. Functional diagram Q10 Q11 Q12 Q13 001aad723 Fig 2. Logic symbol Fig 4. Logic diagram HEF4020B_6 Product data sheet 10 T 14-STAGE COUNTER Fig Rev. 06 — 27 November 2009 HEF4020B 14-stage binary counter Q10 Q11 Q12 Q13 001aad722 CTR14 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 5. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Q3 to Q13 13, 12, 14, 15 Functional description [1] Table 3. Functional table Input HIGH voltage level LOW voltage level don’t care; HEF4020B_6 Product data sheet ...
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... NXP Semiconductors CP input MR input Q10 Q11 Q12 Q13 Fig 6. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I input clamping current IK V input voltage I I output clamping current OK I input/output current ...
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... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage DD V input voltage I T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter V HIGH-level input voltage ...
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... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics for test circuit see SS amb Symbol Parameter Conditions t HIGH to LOW CP to Q0; PHL propagation delay see Qn; see t LOW to HIGH CP to Q0; PLH propagation delay see transition time see t t pulse width CP = HIGH; W minimum width; see MR = HIGH; ...
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... NXP Semiconductors Table 8. Dynamic power dissipation P P can be calculated from the formulas shown Symbol Parameter dynamic power dissipation 12. Waveforms MR INPUT CP INPUT OUTPUT Measurement points are given in Fig 7. Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency Table 9. ...
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... NXP Semiconductors a. Input waveforms b. Test circuit Test data is given in Table Definitions for test circuit: DUT = Device Under Test load capacitance including jig and probe capacitance termination resistance should be equal to the output impedance Z T Fig 8. Test circuit for measuring switching times Table 10. ...
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... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 14. Revision history Table 11. Revision history Document ID Release date _6 HEF4020B 20091127 • Modifications: Section 9 “Recommended operating conditions” _5 HEF4020B 20090707 _4 HEF4020B 20081204 HEF4020B_CNV_3 19950101 HEF4020B_CNV_2 19950101 HEF4020B_6 Product data sheet Data sheet status Change notice Product data sheet - Product data sheet ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Revision history ...