ISL6559 Intersil Corporation, ISL6559 Datasheet
ISL6559
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ISL6559 Summary of contents
Page 1
... Data Sheet Multi-Phase PWM Controller The ISL6559 provides core-voltage regulation by driving interleaved synchronous-rectified buck-converter channels in parallel. Interleaving the channel timing results in increased ripple frequency which reduces input and output ripple currents. The reduction in ripple results in lower component cost, reduced dissipation, and a smaller implementation area ...
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... Block Diagram VID4 VID3 DYNAMIC VID VID2 DAC VID1 VID0 E/A FB COMP x 0.1 OFS 100µA VDIFF 2.2V VSEN DIFF RGND AVERAGE IOUT 2 ISL6559 PGOOD VCC EN 6V POR AND SOFT START 90µ 1 GND FS/DIS 1.23V OSCILLATOR AND SAWTOOTH - + - + I1 I2 CURRENT SENSE & PHASE ...
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... ISEN1 R C COMP PWM2 OFS ISEN2 R OFS FS/DIS PWM3 R T ISEN3 VID4 VID3 VID2 VID1 VID0 PGOOD OVP GND 3 ISL6559 +12V BOOT PVCC UGATE VCC PHASE DRIVER HIP6601B LGATE PWM GND +12V +12V BOOT PVCC NC UGATE VCC PHASE DRIVER HIP6601B LGATE ...
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... OFS Current Offset Accuracy OSCILLATOR Accuracy Adjustment Range Disable Voltage Sawtooth Amplitude Max Duty Cycle 4 ISL6559 Thermal Information Thermal Resistance + 0.3V SOIC Package (Note QFN Package (Note Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Storage Temperature Range . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s 300 ...
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... POWER GOOD AND PROTECTION MONITORS PGOOD Low Voltage Under-Voltage Offset From VID Over-Voltage Threshold OVP Voltage NOTE: 3. These parts are designed and adjusted for accuracy within the system tolerance Functional Pin Description ISL6559CB (28 LEAD SOIC) ISL6559CR (32 LEAD QFN) TOP VIEW 28 EN GND 1 OVP ...
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... The block diagram in Figure 1 provides a top level view of multi-phase power conversion using the ISL6559 controller. Interleaving The switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels ...
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... RMS current for comparison. PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6559 is four. One switching cycle is defined as the time between PWM1 pulse termination signals. The pulse termination signal is an internally generated clock signal which triggers the falling edge of PWM1 ...
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... SAMPLE & ISEN(n) HOLD - R + CHANNEL N LOWER MOSFET ISL6559 INTERNAL CIRCUIT EXTERNAL CIRCUIT FIGURE 3. INTERNAL AND EXTERNAL CURRENT-SENSING CIRCUITRY across the R of the lower MOSFET while it is DS(ON) conducting. The resulting current into the ISEN pin is proportional to the channel current then sampled and held after sufficient settling time every switching cycle ...
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... DAC) plus offset errors in the OFS current source, remote- sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6559 to include all variations in current TABLE 1. VOLTAGE IDENTIFICATION CODES VID3 VID2 VID1 ...
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... Supervising the safe output voltage transition within the DAC range of the processor without discontinuity or disruption. The ISL6559 checks the five VID inputs at the beginning of each channel-1 switching cycle. If the VID code has changed, the controller waits one complete switching cycle to validate the new code ...
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... Enable and Disable The PWM outputs are held in a high-impedance state to assure the drivers remain off while in shutdown mode. Four separate input conditions must be met before the ISL6559 is released from shutdown mode. First, the bias voltage applied at VCC must reach the internal power-on reset (POR) circuit rising threshold ...
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... FB PGOOD will return high once the output voltage surpasses the UV threshold. If the ISL6559 is disabled during operation, the PGOOD signal will not pull low until the output voltage decays below the UV threshold. Over-Voltage Protection UV ...
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... MOSFET or SCR will not overheat before the fuse blows. Once an over-voltage condition is detected, normal PWM operation ceases and PGOOD remains low until the ISL6559 is reset. Cycling the voltage on EN below 1.23V or the bias to VCC below the POR-falling threshold will reset the controller. ...
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... IN higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into 14 ISL6559 separate components involving the upper-MOSFET switching times; the lower-MOSFET body-diode reverse- recovery charge, Q conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground ...
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... The values of the (EQ. 22) compensation components depend on the relationships the L-C pole frequency and the ESR zero frequency. For and (OPTIONAL COMP FB + IOUT V DROOP - VDIFF LOAD-LINE REGULATED ISL6559 CIRCUIT , has already been chosen The target 0 0 ...
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... ISL6559 (EQ. 23) FIGURE 13. COMPENSATION CIRCUIT FOR ISL6559 BASED LC COMPENSATION WITHOUT LOAD-LINE REGULATION The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency type III controller, as shown in Figure 13, provides the ...
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... The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor ac ripple current (see Interleaving and 17 ISL6559 Equation 2), a voltage develops across the bulk-capacitor ESR equal to I (ESR). Thus, once the output capacitors ...
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... Input Supply Voltage Selection The VCC input of the ISL6559 can be connected to either a +5V supply directly or through a current limiting resistor to a +12V supply. An integrated 5.8V shunt regulator maintains the voltage on the VCC pin when a +12V supply is used. A 300Ω resistor is suggested for limiting the current into the VCC pin to approximately 20mA ...
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... IN FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS CURRENT VS DUTY CYCLE FOR SINGLE-PHASE CONVERTER 19 ISL6559 Layout Considerations The following multi-layer printed circuit board layout strategies minimize the impact of board parasitics on converter performance. The following sections highlight some important practices which should not be overlooked during the layout O process ...
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... The ISL6559 can be placed off to one side or centered relative to the individual phase switching components. Routing of sense lines and PWM signals will guide final placement. Critical small signal components to place close to the controller include the ISEN resistors, R feedback resistor, and compensation components. ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. 21 ISL6559 M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 ISL6559 L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...