SST39SF020 Silicon Storage Technology, SST39SF020 Datasheet - Page 3

• Manufacturer Part Number: SST39SF020
• Description: 2 Megabit (256K x 8) Multi-Purpose Flash
• Manufacturer: Silicon Storage Technology

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2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
Toggle Bit (DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and 1’s, i.e., toggling between 0 and 1. The Toggle Bit will
begin with “1”. When the internal Program or Erase opera-
tion is completed, the toggling will stop. The device is then
ready for the next operation. The Toggle Bit is valid after the
rising edge of fourth WE# (or CE#) pulse for Program
operation. For Sector or Chip Erase, the Toggle Bit is valid
after the rising edge of sixth WE# (or CE#) pulse. See
Figure 7 for Toggle Bit timing diagram and Figure 15 for a
flowchart.
Data Protection
The SST39SF020 device provides both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39SF020 provides the JEDEC approved soft-
ware data protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of a series of three byte sequence.
The three byte-load sequence is used to initiate the Pro-
gram operation, providing optimal protection from inad-
vertent write operations, e.g., during the system power-up
© 1998 Silicon Storage Technology, Inc.
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CC
F
UNCTIONAL
Power Up/Down Detection: The write operation is
B
A 17 - A 0
LOCK
6
CC
)
is less than 2.5V.
D
WE#
OE#
CE#
IAGRAM OF
Address Buffers & Latches
6
will produce alternating 0’s
SST39SF020
Control Logic
X-Decoder
3
or power-down. Any Erase operation requires the inclusion
of six byte load sequence. The SST39SF020 device is
shipped with the software data protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode, within TRC.
Product Identification
The product identification mode identifies the device as the
SST39SF020 and manufacturer as SST. This mode may
be accessed by hardware or software operations. The
hardware operation is typically used by a programmer to
identify the correct algorithm for the SST39SF020 device.
Users may wish to use the software product identification
operation to identify the part (i.e., using the device code)
when using multiple manufacturers in the same socket. For
details, see Table 3 for hardware operation or Table 4 for
software operation, Figure 10 for the software ID entry and
read timing diagram and Figure 16 for the ID entry com-
mand sequence flowchart.
Product Identification Mode Exit/Reset
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
internal Program or Erase operation. See Table 4 for
software command codes, Figure 11 for timing waveform
and Figure 16 for a flowchart.
T
ABLE
Manufacturer’s Code
Device Code
1: P
I/O Buffers and Data Latches
RODUCT
2,097,152 bit
DQ 7 - DQ 0
Y-Decoder
EEPROM
Cell Array
I
DENTIFICATION
Address
0000H
0001H
T
326 ILL B1.3
ABLE
BF H
B6 H
Data
326 PGM T1.2
326-10 12/98
5
6
7
8
13
14
15
16
1
2
3
4
9
10
11
12