MT8985 Mitel Networks Corporation, MT8985 Datasheet
MT8985
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MT8985 Summary of contents
Page 1
... Pin PLCC MT8985AL 44 Pin QFP - +85 C Description The MT8985 Enhanced Digital Switch device is an upgraded version of the popular MT8980D Digital Switch (DX pin compatible with the MT8980D and retains all of the MT8980D's functionality. This VLSI device is designed for switching PCM-encoded ...
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... DTA 2-9 3-5 41-43 STi0- 7-11 1-5 STi7 F0i C4i 13-18 15-17 9-11 A0-A5 Address (Inputs). These lines provide the address to MT8985 internal 19-21 13- R/W Read/Write (Input). This input controls the direction of the data bus lines (D0-D7) 2-46 39 STo3 STi3 38 STo4 37 STo5 36 STo6 35 STo7 34 VSS ...
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... ST-BUS and GCI interfaces. Device Operation A functional block diagram of the MT8985 device is shown in Figure 1. The serial ST-BUS streams operate continuously at 2.048 Mb/s and are arranged in 125 s wide frames each containing 32 8-bit channels ...
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... For details on the device addressing, see Software Control and Control register description. Serial Interface Timing The MT8985 master clock (C4i 4.096 MHz allowing serial data link configuration at 2.048 Mb implemented. ...
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... The minimum delay achievable in the MT8985 device is 3 time slots. In the MT8985 device, the information that output in the same channel position as the information is input (position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1) ...
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... Don’t care 2-50 (CML) are output on the ST-BUS output streams once every frame unless the ODE input pin is LOW bit is HIGH, then the MT8985 behaves as if bits of 32 locations 2 (Message Channel) and 0 (Output Enable) of every Connect Memory HIGH (CMH) locations were set to HIGH, regardless of the actual value ...
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... On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially hazardous condition when multiple MT8985 ST-BUS outputs are tied together to form matrices, as these outputs may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition ...
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... Kb/s, ISDN H0 and others), the central all other routing matrix has to guarantee constant throughput delay to maintain the sequence integrity between input and output channels. example where the MT8985 device guarantees data controlling the integrity when data flows from the T1/E1 to the S/U interface links and vice-versa. Modern technologies 0s ...
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... The MT8985 device suits this application and can be used to form a complete non-blocking switch matrix of 512 channels (see Figure 9). ...
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... MT8930B MVIP BUS Server 3 (256 PORT ST-BUS MT8985s (x4) HDLC MT8972B • • or • • ANALOG • MT8985s (x4) MVIP To Video, Data, BUS Fax Services Local Environment Server 3 ST-BUS MH89760B MT8985 MT8985 MT8985 MT8985 MH89790B Dual T1/E1 Card Public Network Access T1 E1 ...
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... Input Streams From MVIP 8 Input On-Board ST-BUS Streams www.DataSheet4U.com FDL HDLC MT8952B T1/E1 MH89760B or MH89790B HDLC MT8952B ANALOG D-PHONE MT8992/93 MT8985 #1 CSTo MVIP Direction MT8985 #2 CSTo MVIP Enable MT8985 #3 MT8985 #4 Figure 9 - 512-Channel Switch Array MVIP HEADER MVIP STo0-7 512 Channel SWITCH Switch Matrix ...
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... MT8985 S INTERFACE www.DataSheet4U.com MT8930B DIGITAL PHONE MT8992/93 Figure 11 - S-Access Card Functional Block Diagram 2-56 MVIP HEADER MVIP STo1-7 STi7-1 SWITCH MATRIX MT8985 STi0 HDLC HDLC PC INTERFACE MVIP STi1-7 STo7-1 STo0 DPLL MT8941 DTMF RECEIVER MT8870 ...
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... 2 Test Point Figure 12 - Output Test Load MT8985 Min Max -0 -0 -0 -65 +150 unless otherwise stated. SS Max Units ...
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... MT8985 AC Electrical Characteristics Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 Frame Pulse width 2 Frame Pulse setup time 3 Frame Pulse hold time 4 STo delay Active to Active 5 STi setup time 6 STi hold time 7 Clock period www.DataSheet4U.com 8 CK Input Low 9 CK Input High 10 Clock Rise/Fall Time † ...
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... Max Units Test Conditions 244 300 ns 122 150 ns 244 ns 190 ns 190 ns 45 100 =5V 5%, V =0V, T =– C bit 1 bit 2 Note: bit 0 identifies the first bit of the GCI frame C4i t t STiH STiS MT8985 =150 pF bit 3 2-59 ...
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... MT8985 AC Electrical Characteristics Characteristics 1 O STo0/7 Delay - Active to High STo0/7 Delay - High Z to Active Output Driver Enable Delay CSTo Output Delay S † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are and are for design aid only: not guaranteed and not subject to production testing. ...
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... =150 122 560 1220 ns 300/370 730/800 155 ns 60 110 =150 CSH t RWH t ADH VALID DATA t t DSW VALID DATA t DHW t DDR t AKH AKD MT8985 =150 pF =150 DHR 2-61 ...
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... MT8985 Notes: www.DataSheet4U.com 2-62 ...