XC2S15-xxxx Xilinx, XC2S15-xxxx Datasheet

XC2S15-xxxx

Manufacturer Part Number

XC2S15-xxxx

Description

Spartan-II 2.5V FPGA Family:Introduction and Ordering Information

Manufacturer

Xilinx

Datasheet

1.XC2S15-XXXX.pdf (4 pages)

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DS001-1 (v2.3) November 1, 2001

Introduction

The Spartan™-II 2.5V Field-Programmable Gate Array fam-

ily gives users high performance, abundant logic resources,

and a rich feature set, all at an exceptionally low price. The

six-member family offers densities ranging from 15,000 to

200,000 system gates, as shown in

mance is supported up to 200 MHz.

Spartan-II devices deliver more gates, I/Os, and features

per dollar than other FPGAs by combining advanced pro-

cess technology with a streamlined Virtex-based architec-

ture. Features include block RAM (to 56K bits), distributed

RAM (to 75,264 bits), 16 selectable I/O standards, and four

DLLs. Fast, predictable interconnect means that successive

design iterations continue to meet timing requirements.

The Spartan-II family is a superior alternative to

mask-programmed ASICs. The FPGA avoids the initial cost,

lengthy

conventional ASICs. Also, FPGA programmability permits

design upgrades in the field with no hardware replacement

necessary (impossible with ASICs).

Features

•

Table 1: Spartan-II FPGA Family Members

DS001-1 (v2.3) November 1, 2001

Preliminary Product Specification

Notes:

XC2S100

XC2S150

XC2S200

XC2S15

XC2S30

XC2S50

Device

Second generation ASIC replacement technology

All user I/O counts do not include the four global clock/user input pins. See details in

Densities as high as 5,292 logic cells with up to

200,000 system gates

Streamlined features based on Virtex architecture

Unlimited reprogrammability

Very low cost

development

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Logic

1,728

2,700

3,888

5,292

Cells

432

972

cycles,

(Logic and RAM)

System Gates

100,000

150,000

200,000

and

15,000

30,000

50,000

Table

inherent

1. System perfor-

risk

12 x 18

16 x 24

20 x 30

24 x 36

28 x 42

(R x C)

8 x 12

www.xilinx.com

Array

1-800-255-7778

CLB

Spartan-II 2.5V FPGA Family:

Introduction and Ordering

Information

Preliminary Product Specification

•

CLBs

1,176

Total

216

384

600

864

System level features

Versatile I/O and packaging

Fully supported by powerful Xilinx development system

SelectRAM+™ hierarchical memory:

Fully PCI compliant

Low-power segmented routing architecture

Full readback ability for verification/observability

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input functions

Abundant registers/latches with enable, set, reset

Four dedicated DLLs for advanced clock control

Four primary low-skew global clock distribution nets

IEEE 1149.1 compatible boundary scan logic

Low cost packages available in all densities

Family footprint compatibility in common packages

16 high-performance interface standards

Hot swap Compact PCI friendly

Zero hold time simplifies system timing

Foundation ISE Series: Fully integrated software

Alliance Series: For use with third-party tools

Fully automatic mapping, placement, and routing

User I/O

Maximum

Available

16 bits/LUT distributed RAM

Configurable 4K bit block RAM

Fast interfaces to external RAM

132

176

196

260

284

Table 3, page

(1)

Distributed RAM

13,824

24,576

38,400

55,296

75,264

6,144

Total

Bits

Block RAM

Total

Bits

16K

24K

32K

40K

48K

56K

Related parts for XC2S15-xxxx

XC2S15-xxxx Summary of contents

Page 1

... XC2S30 972 XC2S50 1,728 XC2S100 2,700 XC2S150 3,888 XC2S200 5,292 Notes: 1. All user I/O counts do not include the four global clock/user input pins. See details in © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...

Page 2

... The Xilinx XC17S00A PROM family is recommended for serial configuration of Spartan-II FPGAs. The In-System Programmable (ISP) XC18V00 PROM family is recom- mended for parallel or serial configuration. CLBs CLBs CLBs CLBs XC2S15 www.xilinx.com 1-800-255-7778 R DLL DLL DS001_01_091800 DS001-1 (v2.3) November 1, 2001 Preliminary Product Specification ...

Page 3

... Device User I/O XC2S15 86 XC2S30 132 XC2S50 176 XC2S100 196 XC2S150 260 XC2S200 284 Notes: 1. All user I/O counts do not include the four global clock/user input pins. DS001-1 (v2.3) November 1, 2001 Preliminary Product Specification Spartan-II 2.5V FPGA Family: Introduction and Ordering Information global clock pins are usable as additional user I/Os when shows the maximum user not used as a global clock pin ...

Page 4

... Device Type Speed Grade Device Ordering Options Device Speed Grade XC2S15 -5 Standard Performance XC2S30 -6 Higher Performance XC2S50 XC2S100 XC2S150 XC2S200 Revision History Version No. Date 2.0 09/18/00 Sectioned the Spartan-II Family data sheet into four modules. Added industrial temperature range information. 2.1 10/31/00 Removed Power down feature. ...

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