UMA1005T Philips Semiconductors (Acquired by NXP), UMA1005T Datasheet - Page 7

• Manufacturer Part Number: UMA1005T
• Description: Dual Low-power Frequency Synthesizer
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
Table 1 Description of symbols used in Fig.4
Notes
1. X = don’t care.
2. Not including reset cycles and fractional-N effects.
Auxiliary variable divider
The input signal on INA is amplified to a logic level by a
single ended input buffer, which accepts LOW level AC
coupled input signals. This input stage is enabled if the
serial control bit EA = 1. Disabling means that all currents
November 1994
NM1
NM2
NM3
NM4
PR
NF
FMOD
LONG
CN
CL
CK
EM
EA
SM
SA
NR
NA
PA
Dual low-power frequency synthesizer
SYMBOL
4 if PR = 11 or 00
4 if PR = 1X
8 if PR = 01
4 if PR
BITS
12
2
3
1
1
8
2
4
1
1
2
2
9
9
1
(1)
01
number of main divider cycles when prescaler is programmed in ratio
R1 (FB1 = 1; FB2 = 0); note 2
number of main divider cycles when prescaler is programmed in ratio
R2 (FB1 = 0; FB2 = 0); note 2
number of main divider cycles when prescaler is programmed in ratio
R3 (FB1 = 0; FB2 = 1); note 2
number of main divider cycles when prescaler is programmed in ratio
R4 (FB1 = 1; FB2 = 1); note 2
prescaler type in use:
fractional-N increment
fraction-N modulus selection flag:
A word format selection flag:
binary current setting factor for main charge pumps
binary acceleration factor for proportional charge pump current
binary acceleration factor for integral charge pump current
main divider enable flag
auxiliary divider enable flag
reference select for main phase detector
reference select for auxiliary phase detector
reference divider ratio
auxiliary divider ratio
auxiliary prescaler mode:
PR = 01; modulus 2 prescaler
PR = 10; modulus 3 prescaler
PR = 11; modulus 4 prescaler
PR = 00; modulus 4 prescaler (inhibit ratio 3)
1 = modulo 8
0 = modulo 5
0 = 24-bit A0 format
1 = 32-bit A1 format
PA = 0; divide-by-4
PA = 1; divide-by-1
7
in the input stage are switched off. A fixed divide by 4 is
enabled if PA = 0. This divider has been optimized to
accept a high-frequency (90 MHz at a supply voltage
range of 4.75 to 5.5 V) input signal. If PA = 1 this divider is
disabled and the input signal is fed directly to the second
FUNCTION
Preliminary specification
UMA1005T