ADC12030CIWM National Semiconductor, ADC12030CIWM Datasheet - Page 3

• Manufacturer Part Number: ADC12030CIWM
• Description: Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
• Manufacturer: National Semiconductor

Connection Diagrams
Ordering Information
Pin Descriptions
CCLK
SCLK
DI
The clock applied to this input controls the
sucessive approximation conversion time
interval and the acquisition time. The rise
and fall times of the clock edges should not
exceed 1 µs.
This is the serial data clock input. The clock
applied to this input controls the rate at
which the serial data exchange occurs. The
rising edge loads the information on the DI
pin into the multiplexer address and mode
select shift register. This address controls
which channel of the analog input multi-
plexer (MUX) is selected and the mode of
operation for the A/D. With CS low the fall-
ing edge of SCLK shifts the data resulting
from the previous ADC conversion out on
DO, with the exception of the first bit of data.
When CS is low continously, the first bit of
the data is clocked out on the rising edge of
EOC (end of conversion). When CS is
toggled the falling edge of CS always clocks
out the first bit of data. CS should be
brought low when SCLK is low. The rise and
fall times of the clock edges should not ex-
ceed 1 µs.
This is the serial data input pin. The data ap-
plied to this pin is shifted by the rising edge
of SCLK into the multiplexer address and
24-Pin Wide Body
SO Packages
Top View
ADC12H030CIWM, ADC12030CIWM
ADC12H032CIWM, ADC12032CIWM
ADC12H034CIN, ADC12034CIN
ADC12H034CIWM, ADC12034CIWM
ADC12H038CIWM, ADC12038CIWM
(Continued)
Industrial Temperature Range
DS011354-8
−40˚C
T
A
+85˚C
3
DO
EOC
CS
Package
M16B
M20B
N24C
M24B
M28B
mode select register. Table 2 through Table
5 show the assignment of the multiplexer
address and the mode select data.
The data output pin. This pin is an active
push/pull output when CS is low. When CS
is high, this output is TRI-STATE. The A/D
conversion result (D0–D12) and converter
status data are clocked out by the falling
edge of SCLK on this pin. The word length
and format of this result can vary (see Table
1 ). The word length and format are con-
trolled by the data shifted into the multi-
plexer address and mode select register
(see Table 5 ).
This pin is an active push/pull output and in-
dicates the status of the ADC12030/2/4/8.
When low, it signals that the A/D is busy with
a conversion, auto-calibration, auto-zero or
power down cycle. The rising edge of EOC
signals the end of one of these cycles.
This is the chip select pin. When a logic low
is applied to this pin, the rising edge of
SCLK shifts the data on DI into the address
register. This low also brings DO out of
TRI-STATE. With CS low the falling edge of
SCLK shifts the data resulting from the pre-
vious ADC conversion out on DO, with the
28-Pin Wide Body
SO Packages
Top View
DS011354-9
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