MT8910-1 Mitel Networks Corporation, MT8910-1 Datasheet - Page 14

• Manufacturer Part Number: MT8910-1
• Description: CMOS St-bus Family Digital Subscriber Line Interface Circuit
• Manufacturer: Mitel Networks Corporation

MT8910-1
Control Register 3
Setting CRS1 and CRS0 to 1, 0, respectively, routes
the input C-channel to Control Register 3, allowing
access to the transmit M-bits as shown in Table 4.
The transmit M-channel is a 4 kbit/s maintenance
channel which may carry the EOC messages (with
overhead) as specified in T1.601-1988. Except for
the CRC bits, the M-bits are treated as a transparent
data channel through the DSLIC. CRC bits will be
generated by the transceiver and will be inserted into
the M-channel during their respective M-bit time
slots. (This implies that all input M-bits which are
defined as CRC bits will be overwritten by the
transceiver.) Structuring of the M-bits is described in
the “Maintenance Channel" section of the functional
description.
Control Words After Reset
Applying a logic low to the MRST pin will result in the
three control registers assuming a reset state.
Following a master reset, the three Control Registers
will take the following states:
9-16
5,4,3
Bit
7,6
Control Register 1:
2
1
0
C7
0
SRID1, SRID0
C6
IS2, IS1, IS0
0
SRID1
CRCERR
bit 7
RxSFIB
Name
RSV
C5
1
C4
SRID0
0
bit 6
IS2
0
0
0
0
1
1
1
1
Received superframe Indication. When low, indicates the beginning of the received superframe.
This bit is low for one ST-BUS frame, then high for 95 ST-BUS frames.
Reserved. Always read a 0.
When “1”, the received CRC code did not match with a locally generated CRC code, indicating
that the received data included an error. When “0”, the received CRC code matched with the
internally generated CRC.
Status Register ID. Always reads 0,0 when Status Register 1 is output.
Internal State Indication.
C3
0
IS1
0
0
1
1
0
0
1
1
C2
0
bit 5
IS2
IS0
0
1
0
1
0
1
0
1
C1
0
Table 5. Status Register 1
C0
0
bit 4
IS1
Definition
Full Reset State
Training with no Basic Frame Sync
Training with Basic Frame Sync but no Superframe Sync
Training with Basic Frame Sync and Superframe Sync
Loss of synchronization after E.C. has converged
NA
Loss of superframe sync after E.C. has converged
Active State
bit 3
Status Register 1
When SRID1=0 and SRID0=0, the contents of
Status Register 1 are being output in the C-channel
allowing the system to monitor the functions
described below. (Refer to Table 5.)
Bits 7 and 6 of Status Register 1, SRID1 and SRID0,
are used to identify which status register is being
carried in the output C-channel.
encoded as follows:
IS0
Description
Control Register 2:
Control Register 3:
SRID1
C7
C7
0
1
0
0
1
1
RxSFIB
C6
C6
0
1
bit 2
SRID0
C5
C5
0
1
0
1
0
1
Preliminary Information
C4
C4
Status Register 1
Status Register 2
Status Register 3
Status Register 4
0
1
Definition
bit 1
RSV
C3
C3
0
1
C2
C2
CRCERR
0
1
bit 0
These bits are
C1
C1
0
1
C0
C0
1
0