MAX456 Maxim, MAX456 Datasheet - Page 4

• Manufacturer Part Number: MAX456
• Description: 8 x 8 Video Crosspoint Switch
• Manufacturer: Maxim

8 x 8 Video Crosspoint Switch
Note 1: Buffer inputs are internally grounded with a 1000 or 1001 command from the D3-D0 lines. AGND must be at 0.0V since the
4
______________________________________________________________Pin Description
25, 27, 29, 31,
13, 15, 17, 19
33, 35, 37, 39
5, 7, 9, 11,
16, 26, 40
28, 30, 32
_______________________________________________________________________________________
3, 4, 6
10, 12
20, 34
DIP
14
18
21
22
23
24
36
38
—
1
2
8
gain setting resistors of the buffers are internally tied to AGND.
PIN
28, 30, 32, 35,
15, 17, 19, 21
37, 39, 41, 43
1, 12, 23, 34
6, 8, 10, 13,
18, 29, 44
31, 33, 36
PLCC
4, 5, 7
11, 14
22, 38
16
20
24
25
26
27
40
42
2
3
9
D1/SER OUT
OUT7-OUT0
EDGE/
D0/SER IN
A2, A1, A0
SER/P
IN0–IN7
LATCH
NAME
DGND
AGND
LOAD
N.C.
WR
V+
C
CE
D3
D2
V-
—
E
–
L
—
–
—
E
A
—
—
V
—
R
–
E
—
–
L
No connect. Not internally connected.
Parallel Data Bit D1 when SER/P
multiple parts when SER/P
Parallel Data Bit D0 when SER/P
SER/P
Output Buffer Address Lines
Video lnput Lines
Asynchronous control line. When LOAD = 1, all the 400Ω internal active
loads are on. When LOAD = 0, external 400Ω loads must be used. The
buffers MUST have a resistive load to maintain stability.
Digital Ground Pins. Both DGND pins must have the same potential and
be bypassed to AGND. DGND should be within ±0.3V of AGND.
When this control line is high, the 2nd-rank registers are loaded with the
rising edge of the LATCH line. If this control line is low, the 2nd-rank reg-
isters are transparant when LATCH is low, passing data directly from the
1st-rank registers to the decoders.
All V+ pins must be tied to each other and bypassed to AGND
separately (Figure 2).
5V = 32-Bit Serial, 0V = 7-Bit Parallel
Both V- pins must be tied to each other and bypassed to AGND
separately (Figure 2).
WRITE in the serial mode, shifts data in. In the parallel mode, WR loads
data into the 1st-rank registers. Data is latched on the rising edge.
If EDGE/
rank registers on the rising edge of LATCH. If EDGE/
loaded while LATCH = 0V. In addition, data is loaded during the execution
of parallel-mode functions 1011 through 1110, or if LATCH = 5V during the
execution of the parallel-mode "software-LATCH" command (1111).
–
C
Chip Enable. When
Output Buffers 7-0 (Note 1)
Analog Ground must be at 0.0V since the gain resistors of the buffers are
tied to these 3 pins.
Parallel Data Bit D3 when SER/
the input channel to be connected to buffer. When D3 = 5V, then D0-D2
specify control codes. D3 is not used when SER/
Parallel Data Bit D2 when SER/
SER/
—
h
—
—
i
p
— —
—
E
—
–
P
—
A
—
—
n
A
—
R
a
–
–
—
L
—
R
–
b
E
—
—
= 5V.
—
l
= 5V.
V
—
e
–
E
—
. When
–
L
= 5V, data is loaded from the 1st-rank registers to the 2nd-
–
C
–
C
—
—
E
E
–
–
= 0V and CE = 5V, the WR line is enabled.
= 0V and CE = 5V, the WR line is enabled.
—
A
—
R
–
–
P
—
FUNCTION
= 5V.
A
—
—
—
–
P
—
A
A
R
—
—
–
A
—
R
R
–
–
R
= 0V. When D3 = 0V, D0-D2 specifies
–
= 0V. Serial Output for cascading
= 0V. A Serial Input when
= 0V. Not used when
–
P
—
A
—
R
–
L
—
–
E
—
= 5V.
V
—
E
—
L
–
= 0V, data is