MAX1204 Maxim, MAX1204 Datasheet - Page 16

• Manufacturer Part Number: MAX1204
• Description: 5v / 8-cHANNEL / sERIAL / 10-bIT adc WITH 3v dIGITAL iNTERFACE
• Manufacturer: Maxim

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
shut down the converter completely. SHDN overrides
bits 1 and 0 of the control byte.
Full power-down mode turns off all chip functions
that draw quiescent current, reducing I
cally to 2µA.
Fast power-down mode turns off all circuitry except the
bandgap reference. With fast power-down mode, the
supply current is 30µA. Power-up time can be shortened
to 5µs in internal compensation mode.
The I
(DIN, SCLK, CS) is held high in either power-down mode.
The actual shutdown current depends on the state of the
digital inputs, the voltage applied to the digital inputs
(V
ature. Figure 12c shows the maximum I
each digital input held high in power-down mode for differ-
ent operating conditions. This current is cumulative, so if
all three digital inputs are held high, the additional shut-
down current is three times the value shown in Figure 12c.
In both software power-down modes, the serial interface
remains operational, but the ADC does not convert.
Table 5 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
delay and maximum sample rate.
In external compensation mode, power-up time is 20ms
with a 4.7µF compensation capacitor (200ms with a 33µF
Table 5. Typical Power-Up Delay Times
Table 6. Software Shutdown and
Clock Mode
16
IH
REFERENCE
), the supply voltage (V
Disabled
Disabled
BUFFER
Enabled
Enabled
Enabled
PD1
______________________________________________________________________________________
DD
1
1
0
0
shutdown current can increase if any digital input
PD0
1
0
1
0
COMPENSATION MODE
REFERENCE-BUFFER
External
Internal
Internal
DD
External clock mode
Internal clock mode
Fast power-down mode
Full power-down mode
), and the operating temper-
DEVICE MODE
DD
DD
and I
increase for
REFERENCE
CAPACITOR
SS
(µF)
4.7
typi-
POWER-DOWN
capacitor) when the capacitor is initially fully discharged.
From fast power-down, start-up time can be eliminated
by using low-leakage capacitors that do not discharge
more than 1/2LSB while shut down. In power-down, the
capacitor has to supply the current into the reference
(typically 1.5µA) and the transient currents at power-up.
Figures 12a and 12b show the various power-down
sequences in both external and internal clock modes.
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify clock mode. When software power-
down is asserted, the ADC continues to operate in the
last specified clock mode until the conversion is com-
plete. The ADC then powers down into a low
quiescent-current state. In internal clock mode, the
interface remains active and conversion results can be
clocked out even though the MAX1204 has already
entered a software power-down.
The first logical 1 on DIN is interpreted as a start bit
and powers up the MAX1204. Following the start bit,
the control byte also determines clock and power-down
modes. For example, if the control byte contains PD1 =
1, the chip remains powered up. If PD1 = 0,
power-down resumes after one conversion.
Table 7. Hard-Wired Shutdown and
Compensation Mode
V
Floating
GND
Fast/Full
STATE
SHDN
DD
MODE
Fast
Fast
Full
Full
Enabled
Enabled
Full
Power-Down
DEVICE
MODE
See Figure 14c
POWER-UP
DELAY (µs)
300
5
2
2
Internal compensation
External compensation
N/A
REFERENCE-BUFFER
Software Power-Down
COMPENSATION
SAMPLING RATE
MAXIMUM
(ksps)
133
133
133
26
26