MAX1112 Maxim, MAX1112 Datasheet - Page 15

• Manufacturer Part Number: MAX1112
• Description: +5V / Low-Power / Multi-Channel / Serial 8-Bit ADCs
• Manufacturer: Maxim

The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on the falling edge of SCLK, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as:
Figure 12a. Continuous Conversions, External Clock Mode, 10 Clocks/Conversion Timing
Figure 12b. Continuous Conversions, External Clock Mode, 16 Clocks/Conversion Timing
SSTRB
DOUT
SCLK
DOUT
SCLK
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after V
The first high bit clocked into DIN after the MSB of a
conversion in progress is clocked onto the DOUT
pin.
DIN
DIN
CS
CS
S
S
1
CONTROL BYTE 0
______________________________________________________________________________________
CONTROL BYTE 0
OR
8
Data Framing
10 1
+5V, Low-Power, Multi-Channel,
DD
S
B7
is applied.
CONVERSION RESULT 0
B7
CONTROL BYTE 1
CONVERSION RESULT 0
B0
If CS is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nized as a start bit; the current conversion is
terminated, and a new one is started.
The fastest the MAX1112/MAX1113 can run is 10
clocks per conversion. Figure 12a shows the serial-
interface timing necessary to perform a conversion
every 10 SCLK cycles in external clock mode.
Many microcontrollers require that conversions occur in
multiples of eight SCLK clocks; 16 clocks per conver-
sion is typically the fastest that a microcontroller can
drive the MAX1112/MAX1113. Figure 12b shows the
serial-interface timing necessary to perform a conver-
sion every 16 SCLK cycles in external clock mode.
8
S
10 1
B0
S
B7
CONTROL BYTE 1
CONVERSION RESULT 1
Serial 8-Bit ADCs
CONTROL BYTE 2
B0
8
10 1
B7
S
CONVERSION RESULT 2
B7
CONVERSION RESULT 1
CONTROL BYTE 3
15