AD9943 Analog Devices, AD9943 Datasheet - Page 13

• Manufacturer Part Number: AD9943
• Description: Complete 10-Bit and 12-Bit/ 25 MHz CCD Signal Processors
• Manufacturer: Analog Devices

INTERNAL REGISTER MAP
All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (AD9943 = 32 LSB clamp level, and
AD9944 = 128 LSB clamp level).
Table 9.
Register Name
Operation
Control
Clamp Level
VGA Gain
A2
0
0
0
0
Address Bits
A1
0
0
1
1
A0
0
1
0
1
Data Bits
D0
D2, D1
D3
D5, D4
D6
D8, D7
D11 to D9
D0
D1
D2
D3
D4
D5
D6
D11 to D7
D7 to D0
D9 to D0
Function
Software Reset (0 = normal operation, 1 = reset all registers to default).
Power-Down Modes (00 = normal power, 01 = standby, 10 = total shutdown).
OB Clamp Disable (0 = clamp on, 1 = clamp off).
Test Mode. Should always be set to 00.
PBLK Blanking Level (0 = blank output to zero, 1 = blank to ob clamp level).
Test Mode 1. Should always be set to 00.
Test Mode 2. Should always be set to 000.
SHP/SHD Input Polarity (0 = active low, 1 = active high).
DATACLK Input Polarity (0 = active low, 1 = active high).
CLPOB Input Polarity (0 = active low, 1 = active high).
PBLK Input Polarity (0 = active low, 1 = active high).
Three-State Data Outputs (0 = outputs active, 1 = outputs three-stated).
Data Output Latching (0 = latched by DATACLK, 1 = latch is transparent).
Data Output Coding (0 = binary output, 1 = gray code output).
Test Mode. Should always be set to 00000.
OB Clamp Level (AD9943: 0 = 0 LSB, 255 = 63.75 LSB,
AD9944: 0 = 0 LSB, 255 = 255 LSB).
VGA Gain (0 = 6 dB, 1023 = 40 dB).
Rev. B | Page 13 of 20
AD9943/AD9944