CMX605P3 CML Microcircuits, CMX605P3 Datasheet - Page 10

• Manufacturer Part Number: CMX605P3
• Description: Digital Line to POTS Interface
• Manufacturer: CML Microcircuits

Digital Line to POTS Interface
1.5.4
This block operates independently and has its own output pin. It can transmit 12kHz or 16kHz and is
controlled by bit 4 of the SETUP Register. Bit 7 of the MODE Register is used to enable or disable this
block. The signal has a rise and fall time each of about 4.5ms. The SPM signal rises from the bias level
to 0dBm in 16 steps of
magnitude.
1.5.5
This block adjusts the amplitude of the FSK transmit signal output level, the level skew between DTMF
tones and the signal routing to the output ports.
Output signal levels are proportional to V
V
The RING signal is digital: a square wave with amplitude of
is not selected, the RING output pin is connected to V
The level attenuator provides for level adjustment from 0dB to -14dB in -2dB steps. The typical level is
determined by bits 2 to 4 of the MODE Register as shown in the table below:
1.5.6
This block connects the µC, via the ‘C-BUS’ interface, to the FSK Encoder.
The block can be programmed to convert transmit data from 8-bit bytes to asynchronous data characters
by adding Start and Stop bits. The transmit data is then passed to the FSK Encoder.
Data to be transmitted should be loaded by the µC into the TX DATA Register when the Tx Data Ready
bit (bit 6) of the STATUS Register goes high. It will then be treated by the Tx UART block in one of two
ways, depending on the setting of bit 1 of the SETUP Register:
DD
2001 Consumer Microcircuits Limited
= 5.0V) are:
SPM Generator
Transmit Signal Control
Tx UART
If bit 1 of the SETUP Register is ‘0’ (Tx Sync mode) then the 8 bits from the TX DATA Register
will be transmitted sequentially at 1200bps, lsb (D0) first.
If bit 1 of the SETUP Register is ‘1’ (Tx Async mode) then bits will be transmitted as
asynchronous data characters at 1200 bps according to the following format:
»
MODE Register
Bit 4
2dB magnitude, and falls from 0dBm to bias level in 16 steps of
0
0
0
0
1
1
1
1
Single Tone
Dual Tone (per tone)
DTMF High Frequency Tone
DTMF Low Frequency Tone
FSK Signal
Bit 3
0
0
1
1
0
0
1
1
DD
. The nominal output signal levels (at 0dB attenuation and
Bit 2
0
1
0
1
0
1
0
1
10
Signal Level Adjustment
SS
.
V
(dB)
-10
-12
-14
DD
-2
-4
-6
-8
0
-3dBm
-3dBm
-5dBm
0dBm
0dBm
peak to peak. When the RING signal
CMX605
D/605/6
»
2dB