IS61C1024AL Integrated Silicon Solution, Inc., IS61C1024AL Datasheet - Page 8

• Manufacturer Part Number: IS61C1024AL
• Description: 128k X 8 High-speed Cmos Static Ram
• Manufacturer: Integrated Silicon Solution, Inc.

8
IS61C1024AL, IS64C1024AL
AC WAVEFORMS
WRITE CYCLE NO. 1
WRITE CYCLE NO. 2
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states
2. I/O will assume the High-Z state if OE = V
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
ADDRESS
ADDRESS
D
D
CE1
CE2
OUT
WE
CE1
CE2
D
OE
OUT
WE
D
IN
IN
LOW
HIGH
t
SA
(CE1 Controlled, OE is HIGH or LOW)
(OE is HIGH During Write Cycle)
DATA UNDEFINED
DATA UNDEFINED
t
SA
IH
.
Integrated Silicon Solution, Inc. — www.issi.com —
VALID ADDRESS
t
t
AW
t
HZWE
HZWE
t
VALID ADDRESS
t
AW
t
t
t
PWE1
WC
PWE1
PWE2
t
t
t
SCE1
SCE2
WC
(1,2)
HIGH-Z
HIGH-Z
(1 )
t
t
SD
DATA
SD
DATA
IN
IN
VALID
VALID
t
t
HD
t
HD
t
LZWE
LZWE
t
t
HA
HA
CE2_WR2.eps
CE2_WR1.eps
ISSI
1-800-379-4774
01/24/05
Rev. B
®