APD-256G064A Vishay, APD-256G064A Datasheet - Page 3

• Manufacturer Part Number: APD-256G064A
• Description: Plasma Panel Display Module, 256 X 64 Graphics Display With Drive Electronics, + 5v Cmos Level Video Interface And Integrated Dc Converter
• Manufacturer: Vishay

Document Number: 37073
Revision 09-Dec-03
DESCRIPTION OF INPUT SIGNALS
DOT CLOCK - This signal enters the SERIAL DATA on each
low to high transition. A total of 256 DOT CLOCK transitions
must be present for each line of column/anode data.
SERIAL DATA - This signal presents the pixel data in positive
logic format. A logic one represents a lit pixel and a logic
zero represents an extinguished pixel. Data is entered from
right to left. The first pixel data entered will represent the
leftmost pixel in the row.
COLUMN LATCH - This signal latches the pixel data into
the driver outputs. When the COLUMN LATCH signal goes
to logic one the data entered previously will fall through to
the driver outputs. When the signal returns to a logic zero,
the data is latched and the shift register is now ready to
accept the next row of data. Must be held low while entering
new SERIAL DATA.
DISPLAY ENABLE - This signal enables the output drivers.
Using a duty cycle control, this signal may also be used for
intensity control. The DISPLAY ENABLE must be at logic
zero before the COLUMN LATCH signal transitions. To avoid
display blurring, the ROW CLOCK signal should also
transition while DISPLAY ENABLE is a logic zero. It is
recommended that this signal remain low for 10µS min.
ROW DATA - This signal is the first line marker for the scan.
This input should be held high to correspond to the first row
of pixel data.
ROW CLOCK - This signal clocks ROW DATA on the falling
edge. The ROW CLOCK signal is repetitive and must be
present for proper scanning of the display module.
The APD-256G064A has a unique input protection circuit
that assures the column drivers stay blanked on power up.
The protection circuit unblanks the column drivers when the
ROW CLOCK signal begins (i.e. the display begins
scanning).
ORDERING INFORMATION
Plasma Display Module with Drivers, CMOS Video Interface, and DC/DC Converter...............................................................APD-256G064A
Data Connector Kit...................................................................................................................................................... ................ 280105-05
Power Connector Kit................................................................................................................................................... ................ 280108-13
Video Controller (+5V) Parallel and Serial Interface...................................................................................................... ................. PDS-500
Video Controller (+12V) Parallel and Serial Interface................................................................................................. ................ PDS-500-1
For Technical Questions, Contact: [e-mail]
PARAMETER
LOGIC AND DATA TIMING
Row Data
Display Enable
Row Clock
Display Enable
Row Clock
Column Latch
Dot Clock
Serial Data
t
t
t
t
t
t
t
1
2
3
4
5
6
7
t
1
1st Bit of Row Will Appear in Leftmost Column
0
MINIMUM
t
6
t
0
5
0
100
25
75
75
—
5
1
1
1
t
1
2
Positive Edge x 256
2
2
TYPICAL
2
APD-256G064A
—
—
—
70
—
—
—
t
4
t
3
254
62
MAXIMUM
62
255
Vishay Dale
200
—
—
—
—
—
—
t
63
7
www.vishay.com
63
0
0
UNITS
1
nS
uS
uS
Hz
nS
nS
nS
1
67