T81L0006B TM Technology Inc., T81L0006B Datasheet - Page 8

• Manufacturer Part Number: T81L0006B
• Description: 8-bit A/d Type Mcu
• Manufacturer: TM Technology Inc.

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Stack Pointer : SP
While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the
stack to begin at locations 08H.
Data Pointer (DPTR) : DPH & DPL
address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
Ports 1.0~1.7 & 2.0,2.1,2.3 & 3.0~3.7
corresponding port output pin to switch high. Writing a zero causes the port output pin to switch low. When used as an input,
the external state of a port pin will be held in the port SFR (i.e., if the external state of a pin is low, the corresponding port
SFR bit will contain a ‘0’; if it is high, the bit will contain a ‘1’).
Serial Data Buffer : SBUF
SBUF, it goes to the transmit buffer and is held for serial transmission. (Moving a byte to SBUF is what initiates the
transmission.) When data is moved from SBUF, it comes from the receive buffer.
Timer Registers : TH0, TL0, TH1, TL1,TH2,TL2
Timer1and Timer2, respectively.
Control Register : IP, IE, TMOD, TCON, SCON, PCON
system, the Timer/Counters, and the serial port. They are described in later sections.
Standard Serial Interface
can commence reception of a second byte before a previously received byte has been read from the register. (However, if the
first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial
port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit
register, and reading SBUF accesses a physically separate receive register.
The serial port can operate in 4 modes:
Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first).
The baud rate is fixed at 1/12 the oscillator frequency.
Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop
bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable.
Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or
1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in
Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the
oscillator frequency.
Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The
baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination
register. Reception is initiated in Mode 0 by the condition RI = ‘0’ and REN = ‘1’. Reception is initiated in the other modes
by the incoming start bit if REN = ‘1’.
TM Technology Inc. reserves the right
to change products or specifications without notice.
The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions.
The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit
All Ports are the SFR latches, respectively. Writing a one to a bit of a port SFR (P1 or P2 or P3) causes the
The Serial Buffer is actually two separate registers, a transmit buffer and a receive buffer. When data is moved to
Register pairs (TH0, TL0) and (TH1, TL1) and (TH2, TL2) are 16-bit Counting registers for Timer/Counters 0 and
.
Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON contain control and status bits for the interrupt
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it
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Publication Date: JAN. 2006
T81L0006A/B
Revsion : C