HMP8115 Intersil Corporation, HMP8115 Datasheet - Page 34

• Manufacturer Part Number: HMP8115
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

15-9
NO.
NO.
NO.
NO.
BIT
BIT
BIT
BIT
7-0
7-0
7-0
8
Reserved
Assert BLANK
Output Signal
Negate BLANK
Output Signal
Negate HSYNC
Output Signal
Horizontal Sync
Detect Window
FUNCTION
FUNCTION
FUNCTION
FUNCTION
This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
start_vertical_blank register.
This 8-bit register specifies the line number to negate BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even
fields. For PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even
fields.
This 8-bit register specifies the horizontal count at which to negate HSYNC each scan
line. Values may range from 0 (0000 0000) to 510 (1111 1111) CLK2 cycles. The leading
edge of HSYNC is count 00
This 8-bit register specifies the width of the window (in 1x clock samples) to look for hor-
izontal sync pulses each line. The window is centered about where the horizontal sync
pulse should be located.
If the horizontal sync pulse falls inside this window, the digital PLL will lock to it. If the hor-
izontal sync pulse falls outside this window, the digital PLL is immediately reset to have
the same timing.
Recommend using a value of 20
TABLE 48. HSYNC DETECT WINDOW REGISTER
TABLE 45. START V_BLANK HIGH REGISTER
TABLE 46. END V_BLANK REGISTER
TABLE 47. END HSYNC REGISTER
SUB ADDRESS = 34
SUB ADDRESS = 35
SUB ADDRESS = 36
SUB ADDRESS = 37
HMP8115
H
.
34
H
to optimize the response time of the digital PLL.
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
0000000
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
FF
12
40
1
B
H
H
H
B