DSPIC30F6015 Microchip Technology Inc., DSPIC30F6015 Datasheet
DSPIC30F6015
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DSPIC30F6015 Summary of contents
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... Microchip Technology Inc. dsPIC30F6010A/6015 Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70150C ...
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... Company’s quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, K EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. ® L ® code hopping devices, Serial EE OQ © 2007 Microchip Technology Inc. ...
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... All DSP instructions single cycle • ±16-bit single-cycle shift © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Timer module with programmable prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • ...
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... This table provides a summary of the dsPIC30F peripheral features. Other available devices in the dsPIC30F Motor Control and Power Conversion Family are shown for feature comparison. DS70150C-page 2 • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • ...
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... SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 FLTA/INT1/RE8 13 FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 Note: Pinout subject to change. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 dsPIC30F6010A EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 ...
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... AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF Note: Pinout subject to change. DS70150C-page 4 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/FLTB/INT2/RD9 42 IC1/FLTA/INT1/RD8 dsPIC30F6015 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 © 2007 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 DS70150C-page 5 ...
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... NOTES: DS70150C-page 6 © 2007 Microchip Technology Inc. ...
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... Reference Manual” (DS70157). © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 This document contains device-specific information for the dsPIC30F6010A and dsPIC30F6015 devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a device block diagram for the dsPIC30F6010A device ...
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... OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6 OC8/UPDN/CN16/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 IC5/RD12 IC6/CN19/RD13 IC7/CN20/RD14 IC8/CN21/RD15 PORTD PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 FLTA/INT1/RE8 FLTB/INT2/RE9 PORTE C1RX/RF0 C1TX/RF1 U1RX/RF2 U1TX/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 PORTF © 2007 Microchip Technology Inc. ...
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... FIGURE 1-2: dsPIC30F6015 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH Program Counter Stack Address Latch Control Control Logic Logic Program Memory (144 Kbytes) Data EEPROM (4 Kbytes) 16 Data Latch ROM Latch Instruction Decode & ...
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... Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Counter Direction State. External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4. Analog = Analog input Output Power © 2007 Microchip Technology Inc. ...
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... ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Description PWM Fault A input. PWM Fault B input. PWM 1 Low output. PWM 1 High output. PWM 2 Low output. PWM 2 High output. PWM 3 Low output. ...
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... UART1 Alternate Receive. UART1 Alternate Transmit. UART2 Receive. UART2 Transmit. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. Analog Voltage Reference (High) input. Analog Voltage Reference (Low) input. Analog = Analog input Output Power © 2007 Microchip Technology Inc. ...
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... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions ...
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... The upper byte of the SR register contains the DSP adder/subtractor Status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address instruction words. © 2007 Microchip Technology Inc. ...
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... AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM ...
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... CLR ED EDAC MAC MOVSAC MPY which MPY.N MSC Selection W0; Rem W1 W1 DSP INSTRUCTION SUMMARY Algebraic Operation – – change – – © 2007 Microchip Technology Inc. ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70150C-page 17 ...
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... OB bits can also optionally generate an arithmetic warn- ing trap when set and the corresponding overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 regis- ter (refer to Section 5.0 “Interrupts”) is set. This allows the user to take immediate action, for example, to correct system gain. © 2007 Microchip Technology Inc. ...
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... No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 2.4.2.2 Accumulator ‘Write-Back’ The MAC class of instructions (with the exception of MPY, MPY ...
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... DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is pre- sented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. © 2007 Microchip Technology Inc. ...
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... TBLRD/TBLWT, which use TBLPAG<7> to determine user or configura- tion space access. In Table 3-1, read/write instructions, bit 23 allows access to the device ID, the user ID and the Configuration bits. Otherwise, bit 23 is always clear. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F6010A/6015 Reset – ...
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... Note: Program Space Visibility cannot be used to access bits <23:16> word in program memory. DS70150C-page 22 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> 0 PSVPAG<7:0> 23 bits Program Counter Select bits 15 bits EA 8 bits 16 bits 24-bit EA <15> <14:1> <0> PC<22:1> 0 Data EA <15:0> Data EA <15:0> Data EA <14:0> 0 Byte Select © 2007 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 A set of table instructions are provided to move byte or word-sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the least significant word of the program address ...
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... Execution prior to exiting the loop due to an Reference interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle Visibility Page register, © 2007 Microchip Technology Inc. ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent Linear Addressing space, X and Y spaces have contiguous addresses. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Program Space 0x0000 (1) PSVPAG ...
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... Optionally Mapped into Program Memory 0xFFFF DS70150C-page 26 Least Significant Byte 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 0x1FFE Y Data RAM (Y) 0x27FE 0x2800 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2007 Microchip Technology Inc. ...
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... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops Read-Only ...
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... Fault. FIGURE 3-8: 15 Byte 1 0001 0x0000 Byte 3 0003 0x0000 Byte 5 0005 0x0000 ® DATA ALIGNMENT MSB LSB Byte 0 0000 Byte 2 0002 Byte 4 0004 © 2007 Microchip Technology Inc. ...
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... Thus, for example desirable to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value, 0x1FFE. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) SR 0042 CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — — XMODSRT 0048 XMODEND 004A ...
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... NOTES: DS70150C-page 32 © 2007 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode, (i.e., address boundary checks will be performed on both the lower and upper address boundaries). © 2007 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags, as well register field to specify the W Address registers ...
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... Bit-Reversed Pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer N bytes, should not be enabled © 2007 Microchip Technology Inc. ...
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... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 4096 2048 1024 512 256 128 © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Bit-Reversed Address Decimal ...
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... NOTES: DS70150C-page 38 © 2007 Microchip Technology Inc. ...
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... The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 • INTTREG<15:0> The associated interrupt vector number and the new CPU interrupt priority level are latched into Vector number (VECNUM< ...
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... C2 – Combined IRQ for CAN2 39 47 PWM – PWM Period Match 40 48 QEI – QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA – PWM Fault FLTB – PWM Fault B 45-53 53-61 Reserved Lowest Natural Order Priority © 2007 Microchip Technology Inc. ...
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... A momentary dip in the power supply to the device has been detected which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority, as shown in Figure 5-1 ...
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... Stack Error Trap Vector Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector Interrupt 52 Vector Interrupt 53 Vector © 2007 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 0x00007E 0x000080 0x000082 0x000084 0x000094 0x0000FE ...
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... The RETFIE (Return from Interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 5.5 Alternate Vector Table In program memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-1 ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F6010A SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF ...
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... TABLE 5-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F6015 SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF IFS1 0086 IC6IF IC5IF IC4IF ...
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... NOTES: DS70150C-page 46 © 2007 Microchip Technology Inc. ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 6.6 “Programming Operations” for further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2007 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2007 Microchip Technology Inc. ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70150C-page 52 © 2007 Microchip Technology Inc. ...
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... The write typically requires complete, but the write time will vary with voltage and temperature. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- ...
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... Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2007 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. © 2007 Microchip Technology Inc. ...
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... WR TRIS WR LAT+ WR Port Read LAT Read Port © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... Typically this instruction would be a NOP will be OL EXAMPLE 8-1: MOV 0xFF00, W0 MOV W0, TRISBB NOP BTSS PORTB, #13 I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; Delay 1 cycle ; Next Instruction © 2007 Microchip Technology Inc. ...
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TABLE 8-1: dsPIC30F6010A PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 TRISA15 TRISA14 — — PORTA 02C2 RA15 RA14 — — LATA 02C4 LATA15 LATA14 — — TRISB 02C6 TRISB15 TRISB14 TRISB13 ...
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... TABLE 8-2: dsPIC30F6015 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 ...
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... CN7IE CN6IE CNEN2 00C2 — — CNPU1 00C4 CN7PUE CN6PUE CNPU2 00C6 — — Legend uninitialized bit TABLE 8-5: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0) FOR dsPIC30F6015 SFR Addr. Bit 7 Bit 6 Name CNEN1 00C0 CN7IE CN6IE CNEN2 00C2 — — CNPU1 00C4 ...
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... NOTES: DS70150C-page 62 © 2007 Microchip Technology Inc. ...
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... Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. ...
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... When a match between the timer and the period regis- ter occurs, an interrupt can be generated, if the respective timer interrupt enable bit is asserted. TSYNC 1 Sync (3) 0 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2007 Microchip Technology Inc. ...
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... XTAL SOSCO pF 100K © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the period register, and is then reset to ‘ ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for ...
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... Interrupt on a 32-bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer ...
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... Timer Configuration bit T32, T2CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70150C-page 68 16 TMR2 Sync LSB PR2 Q D TGATE (T2CON<6> TON 1 x Gate 0 1 Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2007 Microchip Technology Inc. ...
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... FIGURE 10-2: 32-BIT TIMER2/3 BLOCK DIAGRAM FOR dsPIC30F6015 Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) Note: Timer Configuration bit T32, T2CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. © ...
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... TIMER2 BLOCK DIAGRAM (TYPE B TIMER) FOR DSPIC30F6015 Equal Comparator x 16 Reset 0 T2IF Event Flag 1 TGATE Note: The dsPIC30F6015 does not have an external pin input to TIMER2. The following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) DS70150C-page 70 PR2 TMR2 Q D TGATE ...
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... Comparator x 16 Reset 0 T3IF Event Flag 1 TGATE Note: The dsPIC30F6010A/6015 devices do not have an external pin input to Timer3. These modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 PR3 TMR3 Q D TGATE Q CK TON ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T3IE (IEC0<7>). © 2007 Microchip Technology Inc. ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70150C-page 74 © 2007 Microchip Technology Inc. ...
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... TGATE (T4CON<6>) T4CK Note: Timer Configuration bit T45, T4CON(<3>) must be set to ‘ control bits are respective to the T4CON register. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 The Timer4/5 module is similar in operation to the Timer2/3 module. differences, which are listed below: • The Timer4/5 module does not support the ADC Event Trigger feature • ...
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... TCS = 0 and TGATE = 1 (gated time accumulation) DS70150C-page 76 PR4 TMR4 Q D TGATE Q CK TON 1 x Gate Sync PR5 Comparator x 16 TMR5 Q D TGATE Q CK Sync Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2007 Microchip Technology Inc. ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... NOTES: DS70150C-page 78 © 2007 Microchip Technology Inc. ...
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... Timer2 and Timer3 mode selection • Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC30F6010A and dsPIC30F6015 devices have eight capture channels. FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM ICx ...
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... Capture Channel Interrupt Flag is located in the corresponding IFSx STATUS register. Enabling an interrupt is accomplished via the respec- tive Capture Channel Interrupt Enable (ICxIE) bit. The Capture Interrupt Enable bit is located in the corresponding IEC Control register. © 2007 Microchip Technology Inc. defined as ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... NOTES: DS70150C-page 82 © 2007 Microchip Technology Inc. ...
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... These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). dsPIC30F6015 devices have eight compare channels. OCxRS and OCxR in Figure 13-1 represent the Dual Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare ...
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... Fault condition has occurred. This state will be maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits © 2007 Microchip Technology Inc. ...
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... CPU Idle mode if the OCSIDL bit (OCxCON<13> logic 0 and the selected time base (Timer2 or Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
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TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS ...
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... PCDOUT Existing Pin Logic 0 UPDN Up/Down 1 © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • 16-bit up/down position counter • Count direction status • Position Measurement (x2 and x4) mode • ...
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... Position counter reset by detection of index pulse, QEIM<2:0> = 110. 2. Position counter reset by match with MAXCNT, QEIM<2:0> = 111. The x4 Measurement mode provides for finer resolu- tion data (more position counts) for determining motor position. © 2007 Microchip Technology Inc. ...
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... Timer register. When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 In addition, control bit, UDSRC (QEICON<0>), deter- mines whether the timer count direction state is based on the logic state, written into the UPDN control/Status bit (QEICON< ...
Page 92
... The QEI Interrupt Flag bit, QEIIF, is asserted upon occurrence of any of the above events. The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 STATUS register. Enabling an interrupt is accomplished via the respec- tive enable bit, QEIIE. The QEIIE bit is located in the IEC2 Control register. © 2007 Microchip Technology Inc. ...
Page 93
TABLE 14-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN DFLTCON 0124 — — — — — POSCNT 0126 MAXCNT 0128 Legend: u ...
Page 94
... NOTES: DS70150C-page 92 © 2007 Microchip Technology Inc. ...
Page 95
... Three Phase AC Induction Motor • Switched Reluctance (SR) Motor • Brushless DC (BLDC) Motor • Uninterruptible Power Supply (UPS) © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 The PWM module has the following features: • 8 PWM I/O pins with 4 duty cycle generators • 16-bit resolution • ...
Page 96
... PWM Generator Channel 2 Dead-Time #2 Generator and Override Logic PWM Generator Channel 1 Dead-Time #1 Generator and Override Logic Special Event Postscaler PTDIR PWM4H PWM4L PWM3H Output PWM3L Driver Block PWM2H PWM2L PWM1H PWM1L FLTA FLTB Special Event Trigger © 2007 Microchip Technology Inc. ...
Page 97
... Electronically Commutative Motors (ECMs). The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 15.1.1 FREE-RUNNING MODE In the Free-Running mode, the PWM time base counts upwards until the value in the Time Base Period regis- ter (PTPER) is matched ...
Page 98
... Duty Cycle register is greater than the value held in the PTPER register. FIGURE 15-2: EDGE-ALIGNED PWM PTPER PTMR Value 0 Duty Cycle using Period • (PTPER + 1) • 2 • (PTPER + 0.75) • log ( PWM CY log (2) New Duty Cycle Latched © 2007 Microchip Technology Inc. ...
Page 99
... The Duty Cycle registers are 16-bits wide. The LSb of a Duty Cycle register determines whether the PWM edge occurs in the beginning. Thus, the PWM resolution is effectively doubled. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 15.5.1 DUTY CYCLE REGISTER BUFFERS The four PWM Duty Cycle registers are double- buffered to allow glitchless updates of the PWM outputs ...
Page 100
... On a write to the DTCON1 or DTCON2 registers. • On any device Reset. Note: The user should not modify the DTCON1 or DTCON2 values while the PWM mod- ule is operating (PTEN = 1). Unexpected results may occur. © 2007 Microchip Technology Inc ...
Page 101
... PTPER register occurs, the PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Time selected by DTSxI bit ( 15.10 PWM Output Override The PWM output override bits allow the user to manu- ally drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units ...
Page 102
... PWM cycle or half-cycle boundary. The Operating mode for each Fault input pin is selected using the FLTAM and FLTBM control bits in the FLTACON and FLTBCON Special Function Registers. Each of the Fault pins can be controlled manually in software. © 2007 Microchip Technology Inc. ...
Page 103
... PWM time base. If the SEVTDIR bit is set, the special event trigger will occur on the downward count cycle of the PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 15.14.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio ...
Page 104
TABLE 15-2: 8-OUTPUT PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PTMOD4 PTMOD3 ...
Page 105
... The user must perform reads of SPIxBUF if the module is used in a transmit only configuration to avoid a receive overflow condition. (SPIROV = 1) © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) is moved to the receive buffer ...
Page 106
... Shift clock Clock Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Secondary Primary F Prescaler CY Prescaler 1:1-1 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2007 Microchip Technology Inc. ...
Page 107
... Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MSb, even if SSx had been de-asserted in the middle of a transmit/receive. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down ...
Page 108
TABLE 16-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend uninitialized bit Note: ...
Page 109
... I2CRCV is the receive buffer, as shown in Figure 16-1. I2CTRN is the transmit register to which bytes are written during a transmit operation, as shown in Figure 16-2. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 17.1 Operating Function Description The hardware fully implements all the master and slave functions of the I specifications, as well as 7 and 10-bit addressing ...
Page 110
... DS70150C-page 108 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Collision Detect Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2007 Microchip Technology Inc. ...
Page 111
... SCL high (see timing diagram). The inter- rupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 112
... C bus have de-asserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. © 2007 Microchip Technology Inc. ...
Page 113
... Generate a Stop condition on SDA and SCL. 2 • Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 2 17. Master Operation The master device generates all of the serial clock ...
Page 114
... For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle OPERATION DURING CPU C OPERATION DURING CPU IDLE © 2007 Microchip Technology Inc ...
Page 115
TABLE 17-2: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — — I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — I2CCON 0206 I2CEN ...
Page 116
... NOTES: DS70150C-page 114 © 2007 Microchip Technology Inc. ...
Page 117
... Internal Data Bus UTXBRK Data UxTX Parity Note © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 18.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, Odd or No Parity options (for 8-bit data) • ...
Page 118
... Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16X Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA Control Signals UxRXIF © 2007 Microchip Technology Inc. ...
Page 119
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 18.3 Transmitting Data 18.3.1 ...
Page 120
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. © 2007 Microchip Technology Inc. RXB) ...
Page 121
... FERR bit set. The Break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not been received yet. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 122
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. © 2007 Microchip Technology Inc. ...
Page 123
TABLE 18-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG 0212 ...
Page 124
... NOTES: DS70150C-page 122 © 2007 Microchip Technology Inc. ...
Page 125
... This interface/ protocol was designed to allow communications within noisy environments. The dsPIC30F6010A has two CAN modules. The dsPIC30F6015 has only one. The CAN module is a communication controller imple- menting the CAN 2.0 A/B protocol, as defined in the BOSCH specification. The module will support CAN 1 ...
Page 126
... TXB1 Message Queue Control Transmit Byte Sequencer PROTOCOL ENGINE Transmit Logic (1) CiTX Note refers to a particular CAN module (CAN1 or CAN2). The dsPIC30F6015 has only one CAN module. DS70150C-page 124 Acceptance Mask TXB2 RXM0 A Acceptance Filter c RXF0 c e Acceptance Filter p ...
Page 127
... Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 128
... End-of-Frame (EOF) field. Reading the RXnIF flag will indicate which receive buffer caused the interrupt. • Wake-up Interrupt The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. © 2007 Microchip Technology Inc. ...
Page 129
... TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag automatically cleared. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority. ...
Page 130
... By definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 sec, corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point . Also, by definition, Q Sync © 2007 Microchip Technology Inc. ...
Page 131
... SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is initialized by setting SEG2PH<2:0> (CiCFG2<10:8>). The following requirement must be fulfilled while setting the lengths of the Phase Segments: • Propagation Segment + Phase1 Seg > = Phase2 Seg © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 19.6.5 SAMPLE POINT The sample point is the point of time at which the bus ...
Page 132
TABLE 19-1: CAN1 REGISTER MAP FOR dsPIC30F6010A AND 6015 DEVICES SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — C1RXF0SID 0300 C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier<5:0> ...
Page 133
TABLE 19-1: CAN1 REGISTER MAP FOR dsPIC30F6010A AND 6015 DEVICES (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C Transmit Buffer ...
Page 134
TABLE 19-2: CAN2 REGISTER MAP FOR dsPIC30F6010A SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — C2RXF0SID 03C0 C2RXF0EIDH 03C2 — — — — C2RXF0EIDL 03C4 Receive Acceptance Filter 0 Extended Identifier<5:0> — — — ...
Page 135
TABLE 19-2: CAN2 REGISTER MAP FOR dsPIC30F6010A (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C2TX1B1 0416 Transmit Buffer 1 Byte 1 C2TX1B2 0418 Transmit Buffer 1 Byte 3 C2TX1B3 041A Transmit Buffer 1 Byte 5 ...
Page 136
... NOTES: DS70150C-page 134 © 2007 Microchip Technology Inc. ...
Page 137
... The A/D converter has a unique REF REF feature of being able to operate while the device is in Sleep mode. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 The A/D module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • ...
Page 138
... AN10 AN10 AN11 AN11 AN12 AN12 AN13 AN13 AN14 AN14 AN15 AN15 AN1 Note multiplexed with AN0 in the dsPIC30F6015 variant. REF multiplexed with AN1 in the dsPIC30F6015 variant. REF DS70150C-page 136 CH1 ADC S/H - 10-bit Result + CH2 S/H - 16-word, 10-bit + ...
Page 139
... The channels are then converted sequentially. Obvi- ously, if there is only 1 channel selected, the SIMSAM bit is not applicable. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 The CHPS bits selects how many channels are sam- pled. This can vary from channels. If CHPS selects 1 channel, the CH0 channel will be sampled at the sample clock and converted ...
Page 140
... – time AD = 5V). Refer to the Section 24.0 DD under AD A/D CONVERSION CLOCK CALCULATION nsec nsec (30 MIPS – nsec = 2 • – nsec = 4. (ADCS<5:0> nsec = ( nsec © 2007 Microchip Technology Inc. ...
Page 141
... AD 500 ksps Up to 256. 300 ksps Note 1: External V - and V + pins must be used for correct operation. See Figure 20-2 for recommended REF REF circuit. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 R Max V Temperature S DD 500 4.5V to 5.5V -40°C to +85°C 500 4.5V to 5.5V -40°C to +85°C 500 3 ...
Page 142
... Sequential sampling must be used in this configuration to allow adequate sampling time on each input 0 0.1 F 0.01 F © 2007 Microchip Technology Inc. ...
Page 143
... X 750,000 by writing to the ADCS<5:0> control bits in the ADCON3 register • Configure the sampling time writing: SAMC<4:0> = 00010 © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 20.7.3 600 ksps CONFIGURATION GUIDELINE The configuration for 600 ksps operation is dependent on whether a single input pin sampled or whether multiple pins will be sampled ...
Page 144
... Section 24.0 “Electrical Characteristics” for T sample time requirements. ), the S . The HOLD , for 250 IC Sampling Switch leakage V = 0.6V T 500 nA PIN period of sampling AD and HOLD = DAC capacitance = 4 negligible © 2007 Microchip Technology Inc. ...
Page 145
... Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer 0 © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 If the A/D interrupt is enabled, the device will wake-up from Sleep. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set ...
Page 146
... Any external components connected (via high-impedance analog input pin (capacitor, Zener diode, etc.) should have very little leakage current at the pin. and V as ESD the input voltage exceeds this SS © 2007 Microchip Technology Inc. ...
Page 147
TABLE 20-2: ADC REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — — ...
Page 148
... NOTES: DS70150C-page 146 © 2007 Microchip Technology Inc. ...
Page 149
... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 21.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 150
... LP oscillator can be conveniently shared as system clock, as well as Real-Time Clock for Timer1. 3: Any higher will violate PLL input range. 4: Any lower will violate PLL input range. 5: Requires external R and C. Frequency operation MHz. DS70150C-page 148 Description (1) (2) (3) (3) (1) (4) (4) (1)(4) (1) (5) /4 output OSC (5) © 2007 Microchip Technology Inc. ...
Page 151
... FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<5:0> 6 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock ...
Page 152
... OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 OSC2 0 0 OSC2 1 0 CLKO 1 1 CLKO OSC2 0 0 (Note (Note (Note © 2007 Microchip Technology Inc. ...
Page 153
... PLL enters a phase locked state. Should the loop fall out of lock (e.g., due to noise), the lock signal will be rescinded. The state of this signal is reflected in the read-only LOCK bit in the OSCCON register. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 21.2.5 FAST RC OSCILLATOR (FRC) The FRC oscillator is a fast (7.37 MHz nominal) internal RC oscillator ...
Page 154
... Note: The application should not attempt to switch to a clock of frequency lower than 100 kHz when the Fail-Safe Clock Monitor is enabled. If clock switching is performed, the device may generate an oscillator fail trap and switch to the fast RC oscillator. © 2007 Microchip Technology Inc. ...
Page 155
... POR V Rise DD Detect V DD Brown-out Reset BOREN Trap Conflict Illegal Opcode/ Uninitialized W Register © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 21.3 Reset The dsPIC30F differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal ...
Page 156
... Reset vector. The timing for the SYSRST signal is shown in Figure 21-3 through Figure 21-5. T OST T PWRT T OST T PWRT , which is POR s and ensures that the device bias ) is applied. The T parameter PWRT + T . When these delays POR PWRT ) DD ): CASE 1 DD © 2007 Microchip Technology Inc. ...
Page 157
... If the FSCM is disabled and the system clock has not started, the device will frozen state at the Reset vector until the system clock starts. From the user’s perspective, the device will appear Reset until a system clock is available. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 T OST T PWRT 21 ...
Page 158
... Overstress (EOS). Note: Dedicated supervisory devices, such as the MCP1XX and MCP8XX, may also be used as an external Power-on Reset circuit. EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW V POWER-UP MCLR dsPIC30F C power-up slope DD powers DD pin breakdown due to Elec- PP © 2007 Microchip Technology Inc. ...
Page 159
... Illegal Operation Reset 0x000000 Legend unchanged unknown unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR 0 0 ...
Page 160
... All Resets will wake-up the processor from Sleep mode. Any Reset, other than POR, will set the Sleep Status bit POR, the Sleep bit is cleared and T delays are POR LOCK PWRT . PWRT delay and OST POR , POR and T ), the crystal oscillator PWRT © 2007 Microchip Technology Inc. ...
Page 161
... Idle mode upon WDT time-out. The Idle and WDTO Status bits are both set. Unlike wake-up from Sleep, there are no time delays involved in wake-up from Idle. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 21.6 Device Configuration Registers The Configuration bits in each device Configuration ...
Page 162
... PGD and PGC pin functions in all dsPIC30F devices EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/ EMUC3 is selected as the debug I/O pin pair, then a 7-pin interface is required, as the EMUDx/EMUCx pin functions ( are not multiplexed with the PGD and PGC pin functions. © 2007 Microchip Technology Inc ...
Page 163
... PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD Legend uninitialized bit Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 21-8: SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F6015 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST — ...
Page 164
... NOTES: DS70150C-page 162 © 2007 Microchip Technology Inc. ...
Page 165
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Most bit oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 166
... Programmers Reference Manual“ (DS70157). Description {W13, [W13 {0x0000...0x1FFF} {0,1} {0...15} {0...31} {0...255} {0...255} for Byte mode, {0:1023} for Word mode {0...16384} {0...65535} {0...8388608}; LSB must be ‘0’ {-512...511} {-32768...32767} {-16...16} © 2007 Microchip Technology Inc. {0...15} ...
Page 167
... Y data space prefetch address register for DSP instructions {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11+W12], none} Wyd Y data space prefetch destination register for DSP instructions © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0 ...
Page 168
... Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear © 2007 Microchip Technology Inc Status Flags words cycles Affected 1 1 OA,OB,SA, ...
Page 169
... ED Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> Bit Test then Set f ...
Page 170
... Multiply and Subtract from Accumulator {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) W3: WREG © 2007 Microchip Technology Inc Status Flags words cycles Affected 1 ...
Page 171
... Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Description Negate Accumulator WREG = Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) ...
Page 172
... Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Ws © 2007 Microchip Technology Inc Status Flags words cycles Affected 1 1 OA,OB,OAB, SA,SB,SAB ...
Page 173
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 23.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 174
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2007 Microchip Technology Inc. ...
Page 175
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 23.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 176
... Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® battery management, SEEVAL © 2007 Microchip Technology Inc. ...
Page 177
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 (except V and MCLR) (Note 1) ...
Page 178
... OPERATING MIPS VS. VOLTAGE FOR dsPIC30F6010A V Range Temp Range DD (in Volts) (in °C) 4.5-5.5 -40 to +85 4.5-5.5 -40 to +125 3.0-3.6 -40 to +85 3.0-3.6 -40 to +125 2.5-3.0 -40 to +85 TABLE 24-2: OPERATING MIPS VS. VOLTAGE FOR dsPIC30F6015 V Range Temp Range DD (in Volts) (in °C) 4.5-5.5 -40 to +85 4.5-5.5 -40 to +125 3.0-3.6 -40 to +85 3.0-3.6 -40 to +125 2.5-3.0 -40 to +85 TABLE 24-3: THERMAL OPERATING CONDITIONS ...
Page 179
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which V DD © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min ...
Page 180
... OSC1 DD +85°C for Industrial +125°C for Extended 0.128 MIPS LPRC (512 kHz) (1.8 MIPS) FRC (7.37 MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS . DD © 2007 Microchip Technology Inc. ...
Page 181
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 ) IDLE Standard Operating Conditions: 2.5V to 5.5V ...
Page 182
... A 25°C 3.3V A 85°C A 125°C A 25°C A 85° 125° +85°C for Industrial +125°C for Extended (3) Base Power-Down Current (3) Watchdog Timer Current: I WDT (3) Timer1 w/32 kHz Crystal (3) BOR On: I BOR © 2007 Microchip Technology Inc. ...
Page 183
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 184
... -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Osc mode C™ mode (Device not in Brown-out Reset) © 2007 Microchip Technology Inc. ...
Page 185
... I I During Programming EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C T (1) Min ...
Page 186
... DD R Pin L Legend 464 for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 +85°C for Industrial A +125°C for Extended OS31 OS31 OS41 © 2007 Microchip Technology Inc. ...
Page 187
... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 188
... V = 4 +125° 4 +85° 3 +125° 3 +85° 4 +125° 4 +85° 3 +85° 4 +125° 4 © 2007 Microchip Technology Inc. ...
Page 189
... TABLE 24-17: INTERNAL CLOCK TIMING EXAMPLES Clock F OSC Oscillator T CY (1) (MHz) Mode EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F cycle]. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 (3) (3) MIPS MIPS (2) ( sec) w/o PLL w/PLL x4 20.0 0.05 — 1.0 1.0 4.0 0.4 2.5 10.0 0.16 6.25 — 1.0 1.0 4.0 ...
Page 190
... DD T +125° 4.5-5. +125° 4.5-5. +125° 3.0-5. +85° 3.0-3. +125° 3.0-3. +85° 4.5-5. +125° 4.5-5. +85°C for Industrial A +125°C for Extended A Conditions — © 2007 Microchip Technology Inc. ...
Page 191
... Measurements are taken in RC mode and EC mode where CLKO output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 2 ...
Page 192
... RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-2 for load conditions. DS70150C-page 190 SY10 SY20 SY13 SY13 © 2007 Microchip Technology Inc. ...
Page 193
... TABLE 24-22: BAND GAP START-UP TIME REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY40 T Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ Max 2 — ...
Page 194
... Industrial A +125°C for Extended A Max Units Conditions — ns Must also meet parameter TA15 — ns — ns — ns Must also meet parameter TA15 — ns — ns — ns — — prescale value (1, 8, 64, 256) — kHz 1.5 — © 2007 Microchip Technology Inc. ...
Page 195
... TC11 TtxL TxCK Low Time TC15 TtxP TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C Min Typ Synchronous, 0 — ...
Page 196
... Synchronous with prescaler 0 TQ20 +85°C for Industrial A +125°C for Extended A Max Units Conditions — ns Must also meet parameter TQ15 — ns Must also meet parameter TQ15 — ns — 1.5 — — © 2007 Microchip Technology Inc. ...
Page 197
... Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V ...
Page 198
... DS70150C-page 196 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C (1) (2) Min Typ Max — — — — T +85°C for Industrial A T +125°C for Extended A Units Conditions ns — ns — © 2007 Microchip Technology Inc. ...
Page 199
... Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. dsPIC30F6010A/6015 MP30 MP11 MP10 Standard Operating Conditions: 2.5V to 5.5V ...
Page 200
... — — CY +85°C for Industrial A T +125°C for Extended A Units Conditions ns — ns — ns — ns — 16, 32, 64, 128 and 256 (Note 16, 32, 64, 128 and 256 (Note 2) © 2007 Microchip Technology Inc. ...