ST16C654D Exar Corporation, ST16C654D Datasheet
ST16C654D
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ST16C654D Summary of contents
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... Motorola processors. The ST16C654CQ64 (64 pin) offers three state interrupt output ST16C654DCQ64 provides continuous output. The 100 pin package provides additional FIFO status outputs (TXRDY# and RXRDY# A-D), separate infrared transmit data outputs (IRTX A-D) and channel C external clock input (CHCCLK). The ST16C654/654D is compatible with the industry standard ST16C454 and ST16C654/554D ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO IGURE IN UT SSIGNMENT OR TXRDYD# 81 RXRDYD# 82 CDD RID# RXD 85 VCC 86 INTSEL ...
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... O PERATING D EVICE EMPERATURE ART UMBER S TATUS R ANGE 0°C to +70°C Active ST16C654DCQ64 Active ST16C654DIQ64 0°C to +70°C Active ST16C654CQ100 Active ST16C654IQ100 3 ST16C654/654D 68 M LQFP P ODE AND ACKAGES ST16C654 68-pin PLCC Motorola Mode (16/68# pin connected to GND) 48 DSRD# 47 CTSD# 46 DTRD# ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO PIN DESCRIPTIONS Pin Description 64-LQFP 100-QFP 68-PLCC N AME DATA BUS INTERFACE ...
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... To cover this limitation, two 64 pin LQFP packages ver- sions are offered. This pin is bonded to VCC internally in the ST16C654D so the INT outputs operate in the continuous interrupt mode. This pin is bonded to GND internally in the ST16C654 and therefore requires setting MCR bit-3 for enabling the interrupt output pins ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO Pin Description 64-LQFP 100-QFP 68-PLCC N AME FSRS MODEM OR SERIAL I/O INTERFACE TXA 8 17 TXB 10 19 TXC 39 51 ...
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REV. 5.0.2 Pin Description 64-LQFP 100-QFP 68-PLCC N AME RIA RIB RIC RID ANCILLARY SIGNALS XTAL1 25 35 XTAL2 26 36 16/68 ...
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... In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations for the 64 pin 654 this feature is offered by two different LQFP packages. The ST16C654DCV operates in the continuous interrupt enable mode by internally bonding INTSEL to VCC. The ST16C654CV operates in conjunction with MCR bit-3 by internally bonding INTSEL to GND ...
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REV. 5.0.2 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 654 data interface supports the Intel compatible ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 2.2 Device Reset The RESET input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 16). An active high pulse of longer ...
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REV. 5.0.2 2.4 Channels A-D Internal Registers Each UART channel in the 654 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO T 5: TXRDY# ABLE AND FCR -0=0 BIT P INS (FIFO D ) ISABLED byte RXRDY data 0 = THR empty TXRDY byte ...
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REV. 5.0 IGURE AUD ATE Crystal XTAL1 Osc/ XTAL2 Buffer Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling rate. When using a non-standard frequency ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 2.9.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is ...
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REV. 5.0.2 2.10 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO F 10 IGURE ECEIVER PERATION IN 16X Clock Receive Data Shift Register (RSR) 64 bytes by 11-bit wide FIFO Receive Data Byte and Errors 2.11 Auto RTS Hardware Flow ...
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REV. 5.0.2 F 11. A RTS CTS F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# TXB Data Starts RXA ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 2.13 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 654 ...
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REV. 5.0.2 2.15 Infrared Mode The 654 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/ bit ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 2.16 Sleep Mode with Auto Wake-Up The 654 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. ...
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REV. 5.0 IGURE NTERNAL Transmit Shift Register Receive Shift Register 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO OOP ACK IN HANNEL AND VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# CTS# ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each UART channel in the 654 has its own set of configuration registers selected by address lines A0, A1 and A2 with a specific channel selected (See ...
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REV. 5.0.2 T 10: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO T 10: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE EFR RD/WR Auto CTS# Enable 1 0 ...
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REV. 5.0.2 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C654 in the FIFO polled mode of operation. Since the receiver and transmitter ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1) • Logic 0 = Disable the CTS# interrupt (default). • Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# ...
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REV. 5.0 ABLE P ISR R RIORITY EGISTER EVEL ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = Reset the receive ...
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REV. 5.0.2 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • ...
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REV. 5.0.2 MCR[3]: INT Output Enable Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL input, see below table for details. This bit is also used to control the OP2# ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO LSR[1]: Receiver Overrun Flag • Logic overrun error (default). • Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens ...
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REV. 5.0.2 MSR[1]: Delta DSR# Input Flag • Logic change on DSR# input (default). • Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt will ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. T ABLE EFR ...
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REV. 5.0.2 EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is ...
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... Bits 3-0 = Logic 0 Bits 7-4 = Logic levels of the inputs inverted Bits 7-0 = 0xFF Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0xFF RESET STATE Logic 1 Logic 0 Logic 1 Logic 1 Logic 1 Logic 0 ST16C654 = Three-State Condition ST16C654D = Logic 0 Three-State Condition (68 mode, INTSEL = REV. 5.0.2 ...
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REV. 5.0.2 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (64-LQFP) Thermal Resistance (68-PLCC) Thermal Resistance (100-QFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS O U ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE S P YMBOL ARAMETER CLK Clock Pulse Duration OSC Crystal Frequency OSC ...
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REV. 5.0.2 AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE S P YMBOL ARAMETER T Delay From Stop To Set Interrupt SSI T Delay From IOR# To Reset ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO F 15 IGURE ODEM NPUT UTPUT ...
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REV. 5.0 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOW# D0- IGURE ODE OTOROLA A0-A7 T ADS CS# T RWS R/W# T ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO F 19 IGURE ODE OTOROLA A0-A7 Valid Address T ADS CS# T RWS R/W# D0- & I IGURE ECEIVE EADY NTERRUPT RX ...
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REV. 5.0 & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into THR) *INT is cleared when ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO F 23 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX D0:D7 D0: INT RX FIFO fills Trigger Level or RX Data ...
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REV. 5.0 & I IGURE RANSMIT EADY NTERRUPT Stop Start Bit Bit D0:D7 T D0:D7 (Unloading) IER[1] ISR Read enabled INT* TXRDY# IOW# (Loading data into FIFO) *INT cleared when the ISR ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO PACKAGE DIMENSIONS 64 LEAD LOW-PROFILE QUAD FLAT PACK ( 1.4 mm LQFP) A Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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REV. 5.0.2 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC Note: The control dimension is the inch column SYMBOL ...
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ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 100 LEAD PLASTIC QUAD FLAT PACK ( QFP, 1.95 mm Form) 81 100 A A Seating Plane A 1 Note: The control dimension is the millimeter column ...
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... Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP" to "LQFP" consistent with JEDEC and Industry norms. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement ...
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ST16C654/654D REV. 5.0.2 GENERAL DESCRIPTION .................................................................................................1 F .....................................................................................................................................................1 EATURES A ................................................................................................................................................1 PPLICATIONS F 1. ST16C654 B D IGURE LOCK IAGRAM IGURE IN UT SSIGNMENT IGURE IN UT ...
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TO 5.5V QUAD UART WITH 64-BYTE FIFO 4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 26 4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... ABLE NTERRUPT OURCE AND 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 27 T 12: T ...