ST72325R6-AUTO STMicroelectronics, ST72325R6-AUTO Datasheet
ST72325R6-AUTO
Related parts for ST72325R6-AUTO
ST72325R6-AUTO Summary of contents
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MCU for automotive with Kbyte Flash, ADC, Features Memories ■ Kbyte dual voltage High Density Flash (HDFlash) with readout protection capability. In-application programming and in-circuit programming for HDFlash devices ■ 512 to 2048 ...
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... Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.2 Differences between ST72325-Auto and ST72325 datasheets . . . . . . . . 20 1.2.1 1.2.2 1.2.3 2 Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1 Package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3.1 4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 ICP (in-circuit programming 4.6 IAP (in-application programming ...
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ST72325xxx-Auto 6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 Introduction . . . . ...
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Contents 8.4 Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72325xxx-Auto 11.8.1 11.8.2 12 PWM auto-reload timer (ART ...
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Contents 13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72325xxx-Auto 14.6.1 14.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 16.4.1 16.4.2 16.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72325xxx-Auto 18.1.7 18.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 19.7.2 19.7.3 19.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72325xxx-Auto 22 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72325xxx-Auto Table 49. PWM frequency versus resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Table 147. Package selection (OPT7 235 Table 148. Flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Table 149. FASTROM factory coded device types 237 Table 150. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Table 151. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Table 152. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 ...
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ST72325xxx-Auto List of figures Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 49. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72325xxx-Auto Figure 101. 64-pin (10x10) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 ...
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Introduction 1 Introduction 1.1 Description The ST72325-Auto devices are members of the ST7 microcontroller family designed for mid-range automotive applications running from 3.8 to 5.5V. Different package options offer I/O pins. They are derivatives of the ST72321 ...
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... ST72325xxx-Auto Table 1. Device summary (continued) Reference Program memory ST72325R6-Auto Flash 32 Kbytes ST72325R7-Auto Flash 48 Kbytes ST72325R9-Auto Flash 60 Kbytes Figure 1. Device block diagram RESET V PP TLI EVD OSC1 OSC2 PF7:0 (8 bits on R/AR devices) (6 bits on J devices) (5 bits on K devices) PE7:0 (8 bits on R/AR devices) ...
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... Introduction 1.2 Differences between ST72325-Auto and ST72325 datasheets The following sections list the differences between the ST72325-Auto datasheet (version 1) and the ST72325 datasheet (version 3 dated 4 April 2007). 1.2.1 Principal differences Principal differences between the ST72325-Auto datasheet (version 1) and the ST72325 datasheet (version 3 dated 4 April 2007) are listed as follows: 1 ...
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ST72325xxx-Auto 12. Table 137: ADC accuracy on page – added max values specific to 16/32Kbyte Flash devices – removed ROM devices from max values – added conditions to total unadjusted error, to offset error and to gain error 13. Section ...
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Introduction – transferred from cover page to – updated to include only automotive devices – removed ROM from program memory column 3. Figure 1: Device block diagram on page – added R devices to bit counts for ports F, E, ...
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... Note 1 25. Added Figure 104: Flash commercial product code structure on page 237 26. Section 21.3: Development tools on page 27. Table 150: STMicroelectronics development tools on page – removed C and S device versions – added R device version – updated listed tools 28. Table 151: Suggested list of socket types on page 29 ...
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Introduction 5. Table 130: ICCSEL/VPP pin characteristics on page leakage current I 6. Figure 97: Typical A/D converter application on page – changed symbol for ‘input leakage current’ from I – removed I 7. Section 18.1.4: Indexed (no offset, short, ...
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ST72325xxx-Auto 2 Package pinout and pin description 2.1 Package pinout Figure 2. 64-pin LQFP 14x14 and 10x10 package pinout (HS) PE4 1 (HS) PE5 2 (HS) PE6 3 (HS) PE7 4 PWM3 / PB0 5 PWM2 / PB1 6 PWM1 ...
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Package pinout and pin description Figure 3. 44-pin LQFP package pinout RDI / PE1 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 ...
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ST72325xxx-Auto Figure 4. 32-pin LQFP package pinout MCO / AIN8 / PF0 BEEP / (HS) PF1 OCMP1_A / AIN10 / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 For external pin connection guidelines, refer ...
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Package pinout and pin description 2.2 Pin description In the device pin description table, the RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Refer to Chapter ...
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ST72325xxx-Auto Table 2. Device pin descriptions (LQFP64 and LQFP44) (continued) Pin No. Name ( DD_3 ( SS_3 25 15 PF0/MCO/AIN8 26 16 PF1 (HS)/BEEP 27 17 PF2 (HS) PF3/OCMP2_A/ ( AIN9 PF4/OCMP1_A/ ...
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Package pinout and pin description Table 2. Device pin descriptions (LQFP64 and LQFP44) (continued) Pin No. Name 42 30 PC7/SS/AIN15 ( PA0 ( PA1 ( PA2 46 31 PA3 (HS) ( ...
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ST72325xxx-Auto 4. Pull-up always activated on PE2 (see Legend / Abbreviations for Type: Input level: In/Output level: Output level: Port and control configuration: ● Input: ● Output the interrupt input column, “eiX” defines the associated external interrupt vector. ...
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Package pinout and pin description Table 3. Device pin descriptions (LQFP32) Pin No. Name ( AREF ( SSA 3 PF0/MCO/AIN8 I PF1 (HS)/BEEP I PF4/OCMP1_A/AIN10 I PF6 (HS)/ICAP1_A ...
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ST72325xxx-Auto Table 3. Device pin descriptions (LQFP32) (continued) Pin No. Name 21 RESET I SS_2 (2) 23 OSC2 I/O (2) 24 OSC1 I ( DD_2 26 PE0/TDO I PE1/RDI I/O ...
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Package pinout and pin description ● Output the open-drain output column, “T” defines a true open-drain I/O (P-Buffer and protection diode to V implemented). See for more details. 34/250 ana = analog ( open-drain PP = ...
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ST72325xxx-Auto 3 Register and memory map As shown in Figure registers. The available memory locations consist of 128 bytes of register locations Kbytes of RAM and Kbytes of user program memory. The RAM space ...
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Register and memory map Table 4. Hardware register map Address Block Register label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h PBDR 0004h Port B PBDDR 0005h PBOR 0006h PCDR 0007h Port C PCDDR 0008h PCOR 0009h PDDR 000Ah ...
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ST72325xxx-Auto Table 4. Hardware register map (continued) Address Block Register label 0031h TACR2 0032h TACR1 0033h TACSR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch TAIC2HR 003Dh TAIC2LR 003Eh ...
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Register and memory map Table 4. Hardware register map (continued) Address Block Register label 0070h ADCCSR 0071h ADC ADCDRH 0072h ADCDRL 0073h PWMDCR3 0074h PWMDCR2 0075h PWMDCR1 0076h PWMDCR0 0077h PWMCR 0078h PWM ART ARTCSR 0079h ARTCAR 007Ah ARTARR 007Bh ...
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ST72325xxx-Auto 4 Flash program memory 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte basis using ...
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Flash program memory Figure 6. Memory map and sector address 4K 1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh 4.3.1 Readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to ...
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... Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see to the device pinout description ...
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Flash program memory 4.6 IAP (in-application programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user ...
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ST72325xxx-Auto 5 Central processing unit (CPU) 5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 5.2 Main features ● Enable executing 63 basic instructions ● Fast 8-bit by 8-bit ...
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Central processing unit (CPU) 5.3.1 Accumulator (A) The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations. 5.3.2 Index registers (X and Y) These ...
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ST72325xxx-Auto Arithmetic management bits Table 7. Bit Name Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero The result of the ...
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Central processing unit (CPU) The stack pointer is a 16-bit register which is always pointing to the next free location in the stack then decremented after data has been pushed onto the stack and incremented before data is ...
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ST72325xxx-Auto 6 Supply, reset and clock management 6.1 Introduction The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An ...
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Supply, reset and clock management 6.3 Phase locked loop If the clock frequency input to the PLL is in the range MHz, the PLL can be used to multiply the frequency by two to obtain an f ...
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ST72325xxx-Auto Internal RC oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not ...
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Supply, reset and clock management The basic RESET sequence consists of three phases as shown in ● Active phase depending on the RESET source ● 256 or 4096 CPU clock cycle delay (selected by option byte) ● RESET vector fetch ...
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ST72325xxx-Auto The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in Electrical characteristics. If the external RESET pulse is shorter than t ...
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Supply, reset and clock management Figure 14. RESET sequences IT+(LVD) V IT-(LVD) LVD RESET RUN Active Phase EXTERNAL RESET SOURCE RESET PIN WATCHDOG RESET 6.6 System integrity management (SI) The System Integrity Management block contains the Low ...
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ST72325xxx-Auto Provided the minimum V MCU can only be in two modes: – under full software control – in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. ...
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Supply, reset and clock management In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See The interrupt on the rising edge ...
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ST72325xxx-Auto Figure 17. Using the voltage detector to monitor the EVD pin (AVDS bit = 1) V EVD V IT+(EVD) V IT-(EVD) AVDF 0 AVD INTERRUPT REQUEST IF AVDIE = 1 6.6.3 Clock security system (CSS) The Clock Security System ...
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Supply, reset and clock management 6.6.4 Low power modes Table 11. Effect of low power modes on SI Mode Wait No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode. The SICSR register is ...
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ST72325xxx-Auto 6.6.6 System Integrity (SI) Control/Status register (SICSR) SICSR 7 6 AVDS AVDIE RW RW SICSR description Table 13. Bit Name Voltage Detection selection 7 AVDS Voltage Detector interrupt enable 6 AVDIE Voltage Detector flag 5 AVDF LVD reset flag ...
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Supply, reset and clock management SICSR description Table 13. Bit Name Watchdog reset flag 0 WDGRF Table 14. Reset source flags Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog); the LVDRF flag ...
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ST72325xxx-Auto 7 Interrupts 7.1 Introduction The ST7 enhanced interrupt management provides the following features: ● Hardware interrupts ● Software interrupt (TRAP) ● Nested or concurrent interrupt management with flexible interrupt priority and level management: – software programmable ...
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Interrupts Table 15. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Figure 19. Interrupt processing flowchart RESET RESTORE PC FROM STACK Servicing pending interrupts As several ...
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ST72325xxx-Auto When an interrupt request is not serviced immediately latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 1 The hardware priority is exclusive while the software one is ...
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Interrupts flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by ...
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ST72325xxx-Auto Figure 22. Nested interrupt management IT1 IT2 RIM MAIN 7.5 Interrupt register description 7.5.1 CPU CC register interrupt bits CPU Table 16. CPU CC register interrupt bits description Bit Name 5 ...
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Interrupts Table 17. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable 1. TRAP and RESET events can interrupt a level 3 program. 7.5.2 Interrupt software priority registers (ISPRx) These ...
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ST72325xxx-Auto Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x). Table 19. Interrupt dedicated instruction set Instruction HALT Entering Halt mode IRET Interrupt routine return JRM Jump if I1:0 = ...
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Interrupts Table 20. Interrupt mapping Source No. block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt MCC/RTC Main clock controller time base interrupt 1 CSS Safe oscillator activation interrupt 2 ei0 External interrupt port A3..0 3 ei1 ...
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ST72325xxx-Auto To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled ...
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Interrupts 7.6.2 External interrupt control register (EICR) EICR 7 6 IS1[1:0] RW Table 21. EICR register description Bit Name ei2 and ei3 sensitivity 7:6 IS1[1:0] Interrupt polarity for port B 5 IPB ei0 and ei1 sensitivity 4:3 IS2[1:0] Interrupt polarity ...
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ST72325xxx-Auto Table 22. Interrupt sensitivity - ei2 (port B3..0) IS11 IS10 Table 23. Interrupt sensitivity - ei3 (port B4) IS11 IS10 Table 24. Interrupt ...
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Interrupts Table 26. Nested interrupts register map and reset values Address (Hex.) Register label 0024h ISPR0 Reset value 0025h ISPR1 Reset value 0026h ISPR2 Reset value 0027h ISPR3 Reset value EICR 0028h Reset value 70/250 ei1 ...
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ST72325xxx-Auto 8 Power saving modes 8.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Wait), Active Halt and Halt. After a ...
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Power saving modes Figure 25. Slow mode clock transitions 8.3 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals ...
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ST72325xxx-Auto Figure 26. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered ...
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Power saving modes Table 27. MCC/RTC low power mode selection MCCSR OIE bit 0 1 8.4.1 Active Halt mode Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock available entered by ...
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ST72325xxx-Auto Figure 28. Active Halt mode flowchart 1. Peripheral clocked with an external clock source can still be active. 2. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are ...
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Power saving modes ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with Halt mode is configured by the ‘WDGHALT’ option bit of the option byte. The ...
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ST72325xxx-Auto Figure 30. Halt mode flowchart 1. WDGHALT is an option bit. See 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external ...
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Power saving modes Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, re-initialize the corresponding I/O as “Input ...
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ST72325xxx-Auto 9 I/O ports 9.1 Introduction The I/O ports offer different functional modes: ● transfer of data through digital inputs and outputs and for specific pins: ● external interrupt generation ● alternate signal input/output for the on-chip peripherals. An I/O ...
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I/O ports Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity ...
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ST72325xxx-Auto Figure 31. I/O port general block diagram REGISTER ACCESS DR DDR OR OR SEL DDR SEL DR SEL EXTERNAL INTERRUPT SOURCE ( Table 29. I/O port mode options Configuration mode Floating with/without Interrupt Input Pull-up with/without Interrupt ...
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I/O ports Table 30. I/O port configurations NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD 1. When the I/O ...
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ST72325xxx-Auto Caution: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the ...
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I/O ports Table 31. I/O port configuration (continued) Port Pin name PB7, PB3 Port B PB6:5, PB4, PB2:0 Port C PC7:0 Port D PD7:0 PE7:3, PE1:0 Port E PE2 PF7:3 Port F PF2 PF1:0 1. Pull-up is always enabled leading ...
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ST72325xxx-Auto Table 34. I/O port register map and reset values (continued) Address (Hex.) Reset value of all I/O port registers 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h Related documentation SPI Communication between ...
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Watchdog timer (WDG) 10 Watchdog timer (WDG) 10.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its ...
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ST72325xxx-Auto Figure 33. Watchdog block diagram f OSC2 MCC/RTC DIV 64 12-BIT MCC RTC COUNTER MSB 11 6 10.4 How to program the watchdog timeout Figure 34 shows the linear relationship between the 6-bit value to be loaded in the ...
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Watchdog timer (WDG) Figure 35. Exact timeout duration (t WHERE (LSB + 128 min0 t = 16384 x t max0 t = 125ns if f OSC2 CNT = Value of T[5:0] bits in the ...
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ST72325xxx-Auto 10.5 Low power modes Table 35. Effect of low power modes on WDG Mode Slow No effect on Watchdog Wait No effect on Watchdog OIE bit in MCCSR register 0 Halt 0 1 10.6 Hardware watchdog option If Hardware ...
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Watchdog timer (WDG) 10.9 Register description 10.9.1 Control register (WDGCR) WDGCR 7 6 WDGA RW Table 36. WDGCR register description Bit Name Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA ...
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ST72325xxx-Auto 11 Main clock controller with real-time clock and beeper (MCC/RTC) 11.1 Introduction The Main Clock Controller consists of three different functions: ● a programmable CPU clock prescaler ● a clock-out signal to supply external devices ● a real-time clock ...
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Main clock controller with real-time clock and beeper (MCC/RTC) Figure 36. Main clock controller (MCC/RTC) block diagram MCCBCR DIV 64 MCO CP1 MCCSR f OSC2 DIV 11.6 Low power modes Table 38. Effect of low power ...
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ST72325xxx-Auto 11.8 Main clock controller registers 11.8.1 MCC control/status register (MCCSR) MCCSR 7 6 MCO RW Table 40. MCCSR register description Bit Name Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It ...
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Main clock controller with real-time clock and beeper (MCC/RTC) Table 40. MCCSR register description (continued) Bit Name Oscillator interrupt flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the ...
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ST72325xxx-Auto Table 44. Main clock controller register map and reset values Address (Hex.) Register label SICSR 002Bh Reset value MCCSR 002Ch Reset value MCCBCR 002Dh Reset value Main clock controller with real-time clock and beeper (MCC/RTC ...
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PWM auto-reload timer (ART) 12 PWM auto-reload timer (ART) 12.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto- reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five ...
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ST72325xxx-Auto 12.2 Functional description 12.2.1 Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal possible to read or write the contents of ...
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PWM auto-reload timer (ART) Figure 38. Output compare control f COUNTER COUNTER FDh OCRx PWMDCRx PWMx 12.2.5 Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with ...
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ST72325xxx-Auto Figure 39. PWM auto-reload timer function 255 DUTY CYCLE REGISTER (PWMDCRx) AUTO-RELOAD REGISTER (ARTARR) 000 WITH OEx=1 AND OPx=0 WITH OEx=1 AND OPx=1 Figure 40. PWM signal from 0% to 100% duty cycle f COUNTER COUNTER FDh OCRx=FCh OCRx=FDh ...
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PWM auto-reload timer (ART) Figure 41. External event detector example (3 counts EXT COUNTER COUNTER OVF 12.2.8 Input capture function This mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can ...
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ST72325xxx-Auto 12.2.9 External interrupt capability This mode allows the input capture capabilities to be used as external interrupt sources. The interrupts are generated on the edge of the ARTICx signal. The edge sensitivity of the external interrupts is programmable (CSx ...
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PWM auto-reload timer (ART) 12.3 ART registers 12.3.1 Control/status register (ARTCSR) ARTCSR 7 6 EXCL RW Table 45. ARTCSR register description Bit Name External Clock This bit is set and cleared by software. It selects the input clock for the ...
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ST72325xxx-Auto Table 46. Prescaler selection for ART (continued) f COUNTER INPUT INPUT INPUT INPUT f / 128 INPUT 12.3.2 Counter access register (ARTCAR) ARTCAR 7 6 Table 47. ...
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PWM auto-reload timer (ART) Table 49. PWM frequency versus resolution ARTARR value 0 [ 0..127 ] [ 128..191 ] [ 192..223 ] [ 224..239 ] 12.3.4 PWM control register (PWMCR) PWMCR 7 6 Table 50. PWMCR register description Bit Name ...
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ST72325xxx-Auto 12.3.5 Duty cycle registers (PWMDCRx) PWMDCRx 7 6 Table 52. PWMDCRx register description Bit Name Duty Cycle Data 7:0 DC[7:0] A PWMDCRx register is associated with the OCRx register of each PWM channel to determine the second edge location ...
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PWM auto-reload timer (ART) 12.3.7 Input capture registers (ARTICRx) ARTICRx 7 6 Table 54. ARTICRx register description Bit Name Input Capture Data 7:0 IC[7:0] Table 55. PWM auto-reload timer register map and reset values Address (Hex.) Register label PWMDCR3 0073h ...
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ST72325xxx-Auto 13 16-bit timer 13.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals (input capture) ...
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Functional description 13.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. Counter ...
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ST72325xxx-Auto Figure 43. Timer block diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK COUNTER pin REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 (Control Register 1) CR1 (1) ...
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The 16-bit read sequence (from either the Counter Register or the Alternate Counter Register) is illustrated in Figure 44. 16-bit read sequence The user must read the MS Byte first; the LS Byte value is ...
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ST72325xxx-Auto 13.3.2 External clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on ...
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Input capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch ...
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ST72325xxx-Auto 5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. 6 Moreover if one of the ICAPi pins is configured as an input and ...
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Output compare In this section, the index, i, may because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when ...
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ST72325xxx-Auto If the timer clock is an external clock, the formula is: Where: ∆t = Output compare period (in seconds External timer clock frequency (in hertz) CPU Clearing the output compare interrupt request (that is, clearing the OCFi ...
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Figure 50. Output compare block diagram 16-BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit OC1R Register OC2R Register Figure 51. Output compare timing diagram, f OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) Figure ...
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ST72325xxx-Auto 13.3.6 One Pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function ...
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The OC1R register value required for a specific timing application can be calculated using the following formula: Where Pulse period (in seconds CPU clock frequency (in hertz) CPU PRESC = Timer prescaler factor (2, ...
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ST72325xxx-Auto Figure 55. Pulse width modulation mode timing example with 2 output compare functions COUNTER 34E2 Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1 Note: On timers with only one Output Compare register, a fixed ...
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Figure 56. Pulse width modulation cycle flowchart If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2 a continuous signal will ...
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ST72325xxx-Auto 13.4 Low power modes Table 56. Effect of low power modes on 16-bit timer Mode No effect on 16-bit timer. Wait Timer interrupts cause the device to exit from Wait mode. 16-bit timer registers are frozen. In Halt mode, ...
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Table 58. Timer modes Modes One Pulse mode PWM mode 1. See Note 4 in Section 13.3.6 One Pulse mode 2. See Note 5 in Section 13.3.6 One Pulse mode 3. See Note 4 in Section 13.3.7 Pulse ...
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ST72325xxx-Auto Table 59. CR1 register description (continued) Bit Name Forced Output Compare 1 This bit is set and cleared by software. 3 FOLV1 0: No effect on the OCMP1 pin 1: Forces OLVL1 to be copied to the OCMP1 pin, ...
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Table 60. CR2 register description (continued) Bit Name One Pulse Mode 0: One Pulse Mode is not active. 5 OPM 1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the ...
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ST72325xxx-Auto Table 62. CSR register description Bit Name Input Capture Flag 1 7 ICF1 Output Compare Flag 1 6 OCF1 Timer Overflow Flag 5 TOF Input Capture Flag 2 4 ICF2 Output Compare Flag 2 3 OCF2 Timer disable 2 ...
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Input capture 1 low register (IC1LR) This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). IC1LR 7 6 MSB RO RO 13.7.6 Output ...
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ST72325xxx-Auto 13.7.9 Output compare 2 low register (OC2LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC2LR 7 6 MSB RW RW 13.7.10 Counter high register (CHR) This ...
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Alternate counter low register (ACLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR ...
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ST72325xxx-Auto Table 63. 16-bit timer register map and reset values Address Register (Hex.) label Timer A: 32 CR1 Timer B: 42 Reset value Timer A: 31 CR2 Timer B: 41 Reset value Timer A: 33 CSR Timer B: 43 Reset ...
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Serial peripheral interface (SPI) 14 Serial peripheral interface (SPI) 14.1 Introduction The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI ...
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ST72325xxx-Auto Figure 57. Serial peripheral interface block diagram SPIDR Read Buffer MOSI MISO 8-bit Shift Register SOD bit SCK SS 14.3.1 Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure ...
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Serial peripheral interface (SPI) Figure 58. Single master/single slave application MASTER MSBit LSBit 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 14.3.2 Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can ...
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ST72325xxx-Auto Figure 59. Generic SS timing diagram MOSI/MISO Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1) Figure 60. Hardware/Software slave select management 14.3.3 Master mode operation In master mode, the serial clock is output on the SCK pin. ...
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Serial peripheral interface (SPI) 14.3.4 Master mode transmit sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When ...
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ST72325xxx-Auto The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see (OVR) on page 137). 14.4 Clock phase and clock polarity Four ...
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Serial peripheral interface (SPI) Figure 61. Data clock timing diagram SCK (CPOL = 1) SCK (CPOL = 0) MISO MSBit (from master) MOSI MSBit (from slave) SS (to slave) CAPTURE STROBE SCK (CPOL = 1) SCK (CPOL = 0) MISO ...
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ST72325xxx-Auto 14.5 Error flags 14.5.1 Master mode fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: ● The MODF bit is set and an SPI interrupt request ...
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Serial peripheral interface (SPI) Figure 62. Clearing the WCOL bit (Write Collision Flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) Read SPICSR 1st Step 2nd Step Read SPIDR Clearing sequence before SPIF = ...
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ST72325xxx-Auto 14.6 Low power modes Table 64. Effect of low power modes on SPI Mode No effect on SPI. Wait SPI interrupt events cause the device to exit from Wait mode. SPI registers are frozen. In Halt mode, the SPI ...
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Serial peripheral interface (SPI) 14.8 SPI registers 14.8.1 Control register (SPICR) SPICR 7 6 SPIE SPE RW RW Table 66. SPICR register description Bit Name Serial Peripheral Interrupt Enable 7 SPIE Serial Peripheral Output Enable 6 SPE Divider Enable 5 ...
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ST72325xxx-Auto Table 66. SPICR register description (continued) Bit Name Serial Clock Frequency 1:0 SPR[1:0] Table 67. SPI master mode SCK frequency Serial clock f CPU f CPU f CPU f CPU f CPU f CPU 14.8.2 Control/status register (SPICSR) SPICSR ...
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Serial peripheral interface (SPI) Table 68. SPICSR register description (continued) Bit Name Mode Fault flag This bit is set by hardware when the SS pin is pulled low in master mode (see Master mode fault (MODF) on page SPIE = ...
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ST72325xxx-Auto Warning: A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Table 69. SPI register map and reset values Address Register (Hex.) SPIDR 0021h Reset value SPICR ...
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Serial communications interface (SCI) 15 Serial communications interface (SCI) 15.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a ...
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ST72325xxx-Auto 15.3 General description The interface is externally connected to another device by two pins (see ● TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the ...
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Serial communications interface (SCI) Figure 64. SCI block diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU 146/250 Read Received Data Register (RDR) Received Shift ...
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ST72325xxx-Auto 15.4 Functional description The block diagram of the Serial Control Interface, is shown in dedicated registers: ● 2 control registers (SCICR1 and SCICR2) ● a status register (SCISR) ● a baud rate register (SCIBRR) ● an extended prescaler receiver ...
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Serial communications interface (SCI) 15.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the ...
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ST72325xxx-Auto bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle characters Setting the TE bit drives the SCI ...
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Serial communications interface (SCI) When an overrun error occurs: ● The OR bit is set. ● The RDR content is not lost. ● The shift register is overwritten. ● An interrupt is generated if the RIE bit is set and ...
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ST72325xxx-Auto Figure 66. SCI baud rate and extended prescaler block diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 Framing error A framing error is ...
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Serial communications interface (SCI) Conventional baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: with (see SCP[1:0] bits ...
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ST72325xxx-Auto A receiver wakes up by Idle Line detection when the Receive line has recognized an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes up by Address Mark detection ...
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Serial communications interface (SCI) Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. ...
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ST72325xxx-Auto Figure 67. Bit sampling in reception mode RDI LINE Sample clock 15.5 Low power modes Table 71. Effect of low power modes on SCI Mode No effect on SCI. Wait SCI interrupts cause the device to ...
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Serial communications interface (SCI) Table 72. SCI interrupt control/wake-up capability Interrupt event Idle Line Detected Parity Error 15.7 SCI registers 15.7.1 Status register (SCISR) SCISR 7 6 TDRE Table 73. SCISR register description Bit Name Transmit data ...
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ST72325xxx-Auto Table 73. SCISR register description (continued) Bit Name Idle line detect This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register cleared ...
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Serial communications interface (SCI) 15.7.2 Control register 1 (SCICR1) SCICR1 Table 74. SCICR1 register description Bit Name Receive data bit This bit is used to store the 9th bit of the ...
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ST72325xxx-Auto Table 74. SCICR1 register description (continued) Bit Name Parity interrupt enable This bit enables the interrupt capability of the hardware parity control when a parity 0 PIE error is detected (PE bit set set and cleared by ...
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Serial communications interface (SCI) Table 75. SCICR2 register description (continued) Bit Name Receiver enable This bit enables the receiver set and cleared by software Receiver is disabled 1: Receiver is enabled and begins searching for ...
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ST72325xxx-Auto Table 76. SCIBRR register description Bit Name First SCI Prescaler 7:6 SCP[1:0] SCI Transmitter rate divisor 5:3 SCT[2:0] SCI Receiver rate divisor 2:0 SCR[2:0] 15.7.6 Extended receive prescaler division register (SCIERPR) This register allows setting of the extended prescaler ...
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Serial communications interface (SCI) Table 77. SCIERPR register description Bit Name 7:0 ERPR[7:0] 15.7.7 Extended transmit prescaler division register (SCIETPR) This register allows setting of the external prescaler rate division factor for the transmit circuit. SCIETPR 7 6 Table 78. ...
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ST72325xxx-Auto Table 80. SCI register map and reset values Address (Hex.) Register label SCISR 0050h Reset value SCIDR 0051h Reset value SCIBRR 0052h Reset value SCICR1 0053h Reset value SCICR2 0054h Reset value SCIERPR 0055h Reset value SCIPETPR 0057h Reset ...
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I2C bus interface (I2C bus interface (I2C) 16.1 Introduction 2 The I C bus interface serves as an interface between the microcontroller and the serial I bus. It provides both multimaster and slave functions, and controls ...
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ST72325xxx-Auto 16.3 General description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface ...
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I2C bus interface (I2C) 16.3.3 SDA/SCL line control Transmitter mode The interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register. Receiver mode The interface holds the clock line ...
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ST72325xxx-Auto 16.4 Functional description Refer to the CR, SR1 and SR2 registers default the I C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface ...
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I2C bus interface (I2C) Closing slave communication After the last data byte is transferred, a Stop Condition is generated by the master. The interface detects this condition and sets: ● EVF and STOPF bits with an interrupt if the ITE ...
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ST72325xxx-Auto Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. ● In 7-bit addressing mode, one address byte is sent. ● In 10-bit addressing mode, sending the first byte including the ...
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I2C bus interface (I2C) Error cases ● BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set. Note ...
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ST72325xxx-Auto Figure 70. Transfer sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A EV1 EV3 7-bit Master receiver: S Address A EV5 EV6 7-bit Master transmitter: S Address A EV5 EV6 EV8 10-bit Slave ...
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I2C bus interface (I2C) 16.5 Low power modes Table 81. Effect of low power modes on I Mode No effect on I Wait interrupts cause the device to exit from Wait mode registers are ...
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ST72325xxx-Auto 16.7 Register description 2 16.7 control register (CR Reserved - Table 83. CR register description Bit Name 7:6 - Reserved. Forced hardware. Peripheral enable This bit is set and cleared by ...
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I2C bus interface (I2C) Table 83. CR register description (continued) Bit Name Generation of a Stop condition This bit is set and cleared by software also cleared by hardware in master mode. Note: This bit is not cleared ...
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ST72325xxx-Auto Table 84. SR1 register description (continued) Bit Name 10-bit addressing in Master mode This bit is set by hardware when the master has sent the first byte in 10-bit address mode cleared by software reading SR2 register ...
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I2C bus interface (I2C) Table 84. SR1 register description (continued) Bit Name Master/Slave This bit is set by hardware as soon as the interface is in Master mode (writing START = 1 cleared by hardware after detecting a ...
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ST72325xxx-Auto Table 85. SR2 register description (continued) Bit Name Arbitration lost This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE = cleared ...
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I2C bus interface (I2C) Table 86. CCR register description (continued) Bit Name 7-bit clock divider These bits select the speed of the bus (f 6:0 CC[6:0] not cleared when the interface is disabled (PE = 0). Refer to the Note: ...
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ST72325xxx-Auto Table 88. OAR1 register description Bit Name Interface address 7:1 ADD[7:1] Address direction bit 0 ADD0 7:0 ADD[7:0] 2 16.7 own address register (OAR2) OAR2 7 6 FR[1:0] RW Table 89. OAR2 register description Bit Name Frequency ...
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I2C bus interface (I2C) 2 Table 90 register map and reset values Address Register (Hex.) label I2CCR 0018h Reset value I2CSR1 0019h Reset value I2CSR2 001Ah Reset value I2CCCR 001Bh Reset value I2COAR1 001Ch Reset value I2COAR2 001Dh ...
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ST72325xxx-Auto 17 10-bit A/D converter (ADC) 17.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to ...
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A/D converter (ADC) 17.3 Functional description The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V conversion result is ...
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ST72325xxx-Auto 17.3.3 Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the ...
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A/D converter (ADC) Table 92. ADCCSR register description (continued) Bit Name A/D Converter on This bit is set and cleared by software. 5 ADON 0: Disable ADC and stop conversion 1: Enable ADC and start conversion 4 - Reserved. ...
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ST72325xxx-Auto 17.6.3 Data register (ADCDRL) ADCDRL 7 6 Table 94. ADCDRL register description Bit Name 7:2 - Reserved. Forced by hardware to 0. 1:0 D[1:0] LSB of Converted Analog Value 17.6.4 ADC register map and reset values Table 95. ADC ...
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Instruction set 18 Instruction set 18.1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in seven main groups as listed in the following table: Table 96. Addressing modes Inherent Immediate Direct Indexed Indirect Relative ...
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ST72325xxx-Auto Table 97. CPU addressing mode overview (continued) Mode Long Indirect Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Bit Indirect 18.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required ...
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Instruction set 18.1.2 Immediate Immediate instructions have 2 bytes. The first byte contains the opcode and the second byte contains the operand value. Table 99. Immediate instructions Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC 18.1.3 Direct ...
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ST72325xxx-Auto 18.1.5 Indirect (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect (short) The ...
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Instruction set Table 100. Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes (continued) Type Short instructions only 18.1.7 Relative (direct, indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset ...
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ST72325xxx-Auto Table 102. Instruction groups (continued) Group Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification 18.2.1 Using a prebyte The instructions are ...
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Instruction set Table 103. Instruction set overview Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit ...
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ST72325xxx-Auto Table 103. Instruction set overview (continued) Mnemo Description JRUGT Jump JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP ...
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Electrical characteristics 19 Electrical characteristics 19.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 19.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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ST72325xxx-Auto 19.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to ...
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Electrical characteristics 19.2.2 Current characteristics Table 105. Current characteristics Symbol Total current into V ( VDD VSS (source) and V Output current sunk by any standard I/O and control pin I Output current sunk by any high ...
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ST72325xxx-Auto 19.3 Operating conditions 19.3.1 General operating conditions Table 107. General operating conditions Symbol f Internal clock frequency CPU Standard voltage range (except Flash Write/Erase Operating voltage for Flash Write/Erase T Ambient temperature range A Note: Some temperature ...
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Electrical characteristics 19.3.2 Operating conditions with low voltage detector (LVD) Subject to general operating conditions for V Table 108. Operating conditions with low voltage detector (LVD) Symbol Parameter Reset release threshold V IT+(LVD) (V rise) DD Reset generation threshold V ...
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ST72325xxx-Auto 19.3.4 External voltage detector (EVD) thresholds Subject to general operating conditions for V Table 110. External voltage detector (EVD) thresholds Symbol Parameter V 1⇒0 AVDF flag toggle threshold (V IT+(EVD) V 0⇒1 AVDF flag toggle threshold (V IT-(EVD) V ...
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Electrical characteristics 19.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values ...