AMB0480A5 Integrated Device Technology, AMB0480A5 Datasheet - Page 10

• Manufacturer Part Number: AMB0480A5
• Description: Advanced Memory Buffer For Fully Buffered Dimm Modules
• Manufacturer: Integrated Device Technology

PIN DESCRIPTION
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
Channel Interface
DRAM Interface
DDR Compensation
CKE0A-CKE1A,
CKE0B-CKE1B
ODT0A, ODT0B
RASA, RASB
CASA, CASB
BA0A-BA2A,
CS0B-CS1B
CS0A-CS1A,
BA0B-BA2B
WEA, WEB
DDRC_C14
DDRC_B18
DDRC_C18
DDRC_B12
DDRC_C12
A0A-A15A,
DQS[17:0]
A0B-A15B
DQS[17:0]
FBDRES
PN[13:0]
SN[13:0]
DQ[63:0]
CLK[3:0]
PN[13:0]
SN[13:0]
CLK[3:0]
PS[9:0]
SS[9:0]
CB[7:0]
PS[9:0]
SS[9:0]
Signal
Type
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A
A
A
A
A
A
I
I
I
I
Description
Northbound Output Data: High speed serial signal. Read path from AMB toward host on primary side of the DIMM connector.
Northbound Output Data Complement
Northbound Input Data: High speed serial signal. Read path from the previous AMB toward this AMB on secondary side of the DIMM
connector.
Northbound Input Data Complement
Southbound Input Data: High speed serial signal. Write path from host toward AMB on primary side of the DIMM connector.
Southbound Input Data Complement
Southbound Output Data: High speed serial signal. Write path from this AMB toward next AMB on secondary side of the DIMM connector.
These output buffers are disabled for the last AMB on the channel.
Southbound Output Data Complement
External 100Ω precision resistor connected to V
Check bits
Data
Data Strobe: DDR2 data and check-bit strobe.
Data Strobe Complement: DDR2 data and check-bit strobe complements.
Address: Used for providing multiplexed row and column address to SDRAM.
Bank Active: Used to select the bank within a rank.
Row Address Strobe: Used with CS, CAS, and WE to specify the SDRAM command.
Column Address Strobe: Used with CS, RAS, and WE to specify the SDRAM command.
Write Enable: Used with CS, CAS, and RAS to specify the SDRAM command.
Chip Select: Used with CAS, RAS, and WE to specify the SDRAM command. These signals are used for selecting one of two SDRAM
ranks. CS0 is used to select the first rank and CS1 is used to select the second rank.
Clock Enable: DIMM command register enable.
DIMM On-Die-Termination: Dynamic ODT enables for each DIMM on the channel.
Clock: Clocks to DRAMs. CLK0 and CLK1 are always used. CLK2 and CLK3 are used when the AMB is configured for dual rank DIMMs.
Clock Complement: Clocks to DRAMs.
DDR Compensation Common: Common return (ground) pin for DDRC_B18 and DDRC_C18
DDR Compensation Ball Resistor (825Ω) connected to Compensation Common above
DDR Compensation Ball Resistor (121Ω) connected to Compensation Common above
DDR Compensation Ball Resistor (82Ω) connected to V
DDR Compensation Ball Resistor (82Ω) connected to V
CC
10
. On-die termination calibrated against this resistor.
SS
DD
COMMERCIAL TEMPERATURE RANGE