ADT7460 Analog Devices, Inc., ADT7460 Datasheet - Page 22

• Manufacturer Part Number: ADT7460
• Description: Dbcool? Remote Thermal Controller And Fan Controller
• Manufacturer: Analog Devices, Inc.

ADT7460
T
Bit
7
6
5
4
3
2
1
0
Table 24. Status Register 2 (Reg. 0x42)
Bit
7
6
5
4
3
2
1
0
able 23. Status Register 1 (Reg. 0x41)
Mnemonic
OOL
R2T
LT
R1T
-
VCC
-
2.5 V
Mnemonic
D2
D1
F4P
FAN3
FAN2
FAN1
OVT
-
Figure 34. Status Register 2
F4P = 1, FAN 4 OR THERM
Descriptio
Description
1 denotes a bit in Status Register 2 is set
and Status Register 2 should be read.
1 indicates that the Remote 2
temperature high or low limit has been
exceeded.
1 indicates that the Local temperature
high or low limit has been exceeded.
1 indicates that the Remote 1
temperature high or low limit has been
exceeded.
Unused
1 indicates that the VCC high or low
limit has been exceeded.
Unused
1 indicates that the 2.5 V high or low
limit has been exceeded.
TIMER IS OUT-OF-LIMIT
1 indicates an open or short on
D2+/D2− inputs.
1 indicates an o
D2+/D2− inputs.
1 indicates that Fan 4 h
below minimum speed.
indicates that THERM timer limit has
been exceeded if the THERM timer
function is used.
1 indicates that Fan 3 has dropped
below minimum speed.
1 indicates that Fan 2 has dropped
below minimum speed.
1 indicates that Fan 1 has dropped
below minimum speed.
1 indicates that a THERM
overtemperature limit has been
exceeded.
Unused
n
pen or short on
as dropped
Alternatively,
Rev. C | Page 22 of 52
SMBALERT Interrupt Behavior
The ADT7460 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status bits
behave when writing interrupt handler software.
Figure 35 shows how the SMBALERT output and sticky statu
bits behave. Once a limit is exceeded, the corresponding st
bit is set to 1. The status bit remains set until the er
subs
to a
ensures that an out-of-
is p
output remains low fo
of-limit and u
im
HAND
To preve
is r
1.
2
3.
4.
5.
6.
7.
HIGH LIM
TEM
STATUS BIT
SMBALERT
“STICKY”
.
plica
ecom
ollin
s sti
PER
ides
Detect the SMBAL
Enter the interrupt handler.
Read the status registers to identify the inte
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Reg. 0x74, 0x75).
Take the appropriate ac
Exit the inte
Periodically
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
beha
ATURE
tions o
cky si
IT
g the de
LING S
mend
nt the s
and the stat
ve as sh
nce they
Figure 35. SM
ntil the s
n how s
to handl
vice pe
ystem f
MBAL
rrupt handl
own in Figu
poll the status re
us
TEMP BACK IN LIMIT
(S
r the entire dura
oftware handles the interrupt.
remain set until read by software. This
tatus register has been read. This has
register is read
limit event cannot be missed
riodically. Note that the SMBALE
TATUS BIT STAYS SET)
rom being tied up servicing in
e the SMBALERT interrupt as follows:
ERT
ERT INTERRUPTS
BALERT
tion for a given interrupt source.
er.
assertion.
re 36.
and Status Bit Behavior
gisters. If the interrupt status
. The status bits are referred
tion that a reading is out-
(TEMP BE
CLEARED ON READ
rrupt source.
ror condition
LOW LIMIT)
if software
terrupts, it
RT
atus
s