EVB71120 Melexis Company, EVB71120 Datasheet - Page 3

• Manufacturer Part Number: EVB71120
• Description: Evaluation Board For Mlx71120
• Manufacturer: Melexis Company

1
1.1
The MLX71120 receiver architecture is based on a double-conversion super-heterodyne approach. The two
LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency
is derived from a crystal (XTAL). As the first intermediate frequency (IF1) is very high, a reasonably high
degree of image rejection is provided even without using an RF front-end filter. At applications asking for
very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front
of the LNA. The second mixer MIX2 is an image-reject mixer.
The receiver signal chain is setup by one (or two) low noise amplifier(s) (LNA1, LNA2), two down-conversion
mixers (MIX1, MIX2) and an external IF filter with an on-chip amplifier (IFA). By choosing the required
modulation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or
the RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the
demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by
means of the positive and negative peak detectors (PKDET+/-). A digital post-processing of the sliced data
signal can be performed by a noise filter (NF) building block.
The dual LNA configuration can be used for antenna space diversity or antenna frequency diversity or to
setup an LNA cascade (to further improve the input sensitivity). The two LNAs can also be setup to feed the
RF signal differentially.
A sequencer circuit (SEQ) controls the timing during start-up. This is to reduce start-up time and to minimize
power dissipation.
A clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a
microcontroller. The clock output is open drain and gets activated through a load connected to positive
supply.
1.2
! Input frequency ranges: 300 to 470MHz
! Power supply range: 2.1 to 5.5V
! Temperature range: -40 to +125°C
! Shutdown current: 50 nA
! Operating current: 6.5 to 8.1mA
! Selectable IF2 frequency: 10.7MHz or 455kHz
! FSK deviation range: ±10kHz to ±100kHz (WB)
Note:
39012 71120 01
Rev. 003
! Input Sensitivity: at 4kbps NRZ, BER = 3·10
ASK
FSK
Theory of Operation
General
Technical Data Overview
- Sensitivities given for RF input 1 (without SAW filter)
- Sensitivity for RF input 2 is about 2 to 3dB worse (because of SAW filter loss)
wide band 180kHz BW, IF2=10.7MHz
wide band 180kHz BW, IF2=10.7MHz
narrow band 20kHz BW, IF2=455kHz
Frequency
Δf = ±20kHz
Δf = ±5kHz
±2kHz to ±10kHz (NB)
610 to 930MHz
-3
Page 3 of 18
315 MHz
-109dBm
-114dBm
-113dBm
! Image rejection:
! Maximum data rate: 50kps RZ (bi-phase) code,
! Spurious emission: < -54dBm
! Linear RSSI range: > 70dB
! Crystal reference frequency: 16 to 27MHz
! MCU clock frequency: 2.0 to 3.4
Evaluation Board Description
65dB 1
25dB 2
-108dBm
-112dBm
-113dBm
433 MHz
st
nd
300 to 930MHz Receiver
IF (with external RF front-end filter)
IF (internal image rejection)
100kps NRZ
-106dBm
-111dBm
-111dBm
868 MHz
EVB71120
EVB Description
915 MHz
-104dBm
-109dBm
-109dBm
Jan/08