FMS6501 Fairchild Semiconductor, FMS6501 Datasheet - Page 8

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FMS6501

Manufacturer Part Number
FMS6501
Description
12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2004 Fairchild Semiconductor Corporation
FMS6501 Rev. 1.0.4
I
2
Start and Stop Conditions
The data and clock lines remain HIGH when the bus is
not busy. A HIGH-to-LOW transition of the data line,
while the clock is HIGH, is defined as START condition
Operation
The I
ification for Standard Mode. Individual addresses may
be written. There is no read capability. The interface
consists of two lines. These is a serial data line (SDA)
and a serial clock line (SCL), both of which must be
connected to a positive supply through an external
resistor. Data transfer may be initiated only when the
bus is not busy.
C Interface
2
C-compatible interface conforms to the I
SDA
SCL
START condition
SDA
SCL
S
Figure 5. Definition of START and STOP conditions
Data line
stable;
data valid
Figure 4. Bit Transfer
2
C spec-
Change
of data
allowed
8
(S). A LOW-to-HIGH transition of the data line, while
the clock is HIGH, is defined as STOP condition (P).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during
the HIGH period of the clock pulse. Changes in the line
during this time are interpreted as a control signal.
STOP condition
P
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